Abstract: Systems and methods for handling macro compatibility for documents at a storage system are provided. A document to be stored on a network-based storage system is identified. The document is created using a first document processing application that uses a first programming language that is incompatible with the network-based storage system. The document includes macros in the first programming language. A semantic context for an object included in a macro is determined. The macro defines a function to be performed with respect to the object. In response to a determination, based on the semantic context of the object, that the object corresponds to multiple object types, a set of candidate object types for the object is identified. The function is converted into multiple sets of operations represented in a second programming language.

Abstract: In an example, a machine learning (ML) processor emulator can be configured to emulate a legacy processor for emulating a legacy program. The emulator environment can include virtual registers storing operand data on which an operation is to be performed based on a respective instruction from instruction data representative of the legacy program. The ML processor emulator includes a processor ensemble engine that includes ML modules generated by a different ML algorithm, and a voting engine. Each ML module can be configured to emulate an instruction set of a processor and process the operand data according to the operation of the respective instruction to produce a set of candidate result data. The voting engine can be configured to identify a subset of candidate result data from the set of candidate result data and provide output data with content similar to the subset of candidate result data.

Abstract: A multi-chip module includes a first Integrated Circuit (IC) die a second IC die. The first IC die includes an array of first bond pads, a plurality of first code group circuits, and first interleaved interconnections between the plurality of first code group circuits and the array of first bond pads, the first interleaved interconnections including a first interleaving pattern causing data from different code group circuits to be coupled to adjacent first bond pads. The second IC die includes a second array of bond pads that electrically couple to the array of first bond pads, a plurality of second code group circuits, and second interleaved interconnections between the plurality of second code group circuits and the array of second bond pads, the second interleaved interconnections including a second interleaving pattern causing data from different code groups to be coupled to adjacent second bond pads.

Abstract: A discrete 3-D processor comprises first and second dice. The first die comprises three-dimensional memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). The first die does not comprise the off-die peripheral-circuit component. The first and second dice are communicatively coupled by a plurality of inter-die connections. The preferred discrete 3-D processor can be applied to mathematical computing, computer simulation, configurable gate array, pattern processing and neural network.

Abstract: The invention discloses a data structure-aware prefetching method and device on a graphics processing unit. The method comprises the steps of acquiring information for a memory access request in which a monitoring processor checks a graph data structure and read data, using a data structure access mode defined by a breadth first search and graph data structure information to generate four corresponding vector prefetching requests and store into a prefetching request queue. The device comprises a data prefetching unit distributed into each processing unit, each data prefetching unit is respectively connected with an memory access monitor, a response FIFO and a primary cache of a load/store unit, and comprises an address space classifier, a runtime information table, prefetching request generation units and the prefetching request queue.

Abstract: Throttling recommendations for a systolic array may be arbitrated. Throttling recommendations may be received at an arbiter for a systolic array from different sources, such as one or more monitors implemented in an integrated circuit along with the systolic array or sources external to the integrated circuit with the systolic array. A strongest throttling recommendation may be selected. The rate at which data enters the systolic array may be modified according to the strongest throttling recommendation.

Abstract: The present invention provides a method for collecting system logs, applied to an intelligent device with an Android system, wherein providing a daemon process for log collecting, and the daemon process is started when the system of an Android device is started; providing an application process for log processing; providing an external storage device for accessing the intelligent device; the method comprises the following steps: the daemon process collects the application framework layer and logs of the Linux kernel, and saves the logs in a first storage path of the Android system; the application process creating a second storage path in the external storage device after identifying the accessed external storage device; and the application process obtaining the logs from the first storage path and saving the logs in the second storage path.

Abstract: A programmable slave circuit on a communication bus is provided. In a non-limiting example, the communication bus can be a radio frequency front-end (RFFE) bus operating based on a master-slave topology and the programmable slave circuit can be an RFFE slave circuit on the RFFE bus. The programmable slave circuit is configured to receive a high-level command(s) (e.g., a macro word) over the communication bus. A processing circuit in the programmable slave circuit is programmed to generate a low-level command(s) (e.g., a bitmap word) for controlling a coupled circuit(s) based on the high-level command(s). In this regard, it is possible to program or reprogram the processing circuit, for example via over-the-air (OTA) updates, based on the high-level command(s) to be supported, thus making it possible to flexibly customize the programmable slave circuit according to operating requirements and configurations.

Abstract: A convolutional neural network processor includes an information decode unit and a convolutional neural network inference unit. The information decode unit is configured to receive a program input and weight parameter inputs and includes a decoding module and a parallel processing module. The decoding module receives the program input and produces an operational command according to the program input. The parallel processing module is electrically connected to the decoding module, receives the weight parameter inputs and includes a plurality of parallel processing sub-modules for producing a plurality of weight parameter outputs. The convolutional neural network inference unit is electrically connected to the information decode unit and includes a computing module. The computing module is electrically connected to the parallel processing module and produces an output data according to an input data and the weight parameter outputs.

Abstract: A CPU module (100) includes a first bus complying with a first communication protocol, and a second bus complying with a second communication protocol different from the first communication protocol. A conversion setting storage (110) included in the CPU module (100) stores information indicating association between a general instruction complying with the first communication protocol and a dedicated instruction complying with the second communication protocol. A protocol converter (160) included in the CPU module (100) acquires, when the general instruction is output by instruction output means to a device connected via the second bus, the dedicated instruction associated with the general instruction from the conversion setting storage (110) and provides the acquired dedicated instruction to the device via the second bus.

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

Abstract: A processor is described that includes a plurality of compute units. One or more test pattern generators generates one or more test patterns and inputs the one or more test patterns into one or more of the plurality of compute units during testing, which testing includes processing of the one or more test patterns by one or more of the plurality of compute units. One or more control and sequencing logic units identifies an idle period during normal use of the processor in which a compute unit of the plurality of compute units is idle. The one or more control and sequencing units controls the test pattern generator to generate and input the one or more test patterns to the idle compute unit and controls the compute unit to process the one or more test patterns during the idle period. One or more comparators compares a result of testing with an expected result of testing to determine if the compute unit is functioning correctly.

Abstract: A method includes receiving, by a first stage in a pipeline, a first transaction from a previous stage in pipeline; in response to first transaction comprising a high priority transaction, processing high priority transaction by sending high priority transaction to a buffer; receiving a second transaction from previous stage; in response to second transaction comprising a low priority transaction, processing low priority transaction by monitoring a full signal from buffer while sending low priority transaction to buffer; in response to full signal asserted and no high priority transaction being available from previous stage, pausing processing of low priority transaction; in response to full signal asserted and a high priority transaction being available from previous stage, stopping processing of low priority transaction and processing high priority transaction; and in response to full signal being de-asserted, processing low priority transaction by sending low priority transaction to buffer.

Abstract: A docking station for receiving different types of seismic nodes, the docking station including a frame; a control module attached to the frame plural docking modules attached to the frame, wherein each docking module includes plural docking bays; a monitor attached to the frame and configured to display information about the plural docking modules; and a network connection device attached to the frame and configured to provide data transfer capabilities for each docking bay of the plural docking bays. The plural docking bays are configured to accept interchangeable ports that are compatible with the different types of seismic nodes.

Abstract: Various embodiments of the present technology generally relate to methods and systems for providing a flexible, updatable, and backward compatible programmable logic controller (“PLC”) and instruction set library. The instruction set library in the PLC can be updated without downtime of the PLC or the machines controlled by the PLC. The instruction set library is decoupled from the PLC firmware and bound via an API so that instructions in the executable code are bound to the firmware such that updates to the instruction set library can happen between scans of the executable without requiring the firmware be updated. Further, the instruction set library may be partitioned to limit updates and the amount of the complete instruction set library that is stored on the PLC to only those used by the PLC.

Abstract: An execution method comprises the following operations: —every time an instruction to be protected of a preceding basic block is loaded, constructing a new value of a signature of this preceding basic block from the value of this instruction to be protected and the preceding value of the signature. The method further includes loading an initialization vector contained in a subsequent basic block and calculating, from said loaded initialization vector, a value reached for signing the preceding basic block. The method also includes comparing the constructed value of the signature with the expected value of this signature, and—only if these values do not match, triggering the signaling of a fault during the execution of the machine code.

Abstract: The technology disclosed herein pertains to a system and method for profiling performance of an embedded computation instruction set (CIS), the method including receiving a profiling component to a computational storage device (CSD), the profiling component being configured to measure one or more execution parameters of a computational instruction set (CIS), executing the CIS at a program slot in a computational storage processor of the CSD, monitoring the execution of the CIS to generate a log of the execution parameters of the CIS, and communicating the log to a host in response to receiving a get-log page command.

Abstract: A method is described for identifying communication-ready data bus subscribers connected to a local bus. The method comprises receiving, at a local bus master, at least one data packet transmitted via the local bus, wherein the at least one data packet received at the local bus master comprises an address of a communication-ready data bus subscriber among a plurality of communication-ready data bus subscribers in the local bus, wherein the communication-ready data bus subscriber is in a sequence of communication-ready data bus subscribers, and mapping of the received address by the local bus master to a relative position of the communication-ready data bus subscriber in the sequence of communication-ready data bus subscribers in the local bus. In addition, a local bus master of the local bus is described.

Abstract: An arithmetic processing device includes a plurality of arithmetic processing circuitry, each of which includes: an instruction hold circuit configured to hold an arithmetic instruction; an arithmetic circuit configured to execute an arithmetic instruction issued from the instruction hold circuit; and a measurement circuit configured to measure a predetermined time period, wherein the instruction hold circuit is configured to perform first processing after the instruction hold circuit holds a first arithmetic instruction when the arithmetic circuit is not executing other arithmetic instructions, the first processing being configured to: cause the measurement circuit to initiate the measurement of the predetermined time; and issue, in response to a completion of the measurement of the predetermined time period, the held first arithmetic instruction to the arithmetic circuit, and wherein the predetermined time period measured by the measurement circuit is different between at least two of the plurality of arith

Abstract: Systems, methods, apparatuses, and computer program products for packet latency reduction in mobile radio access networks. One method may include, when a buffer of a first sublayer of a wireless access link is empty and there is a new data unit in the first sublayer or when the first sublayer buffer is not empty and a data unit leaves a second sublayer buffer, comparing the number of data units currently stored in the second sublayer buffer with a queue length threshold that defines a total amount of space in the second sublayer buffer. When the number of data units currently stored in the second sublayer buffer is less than the queue length threshold, the method may also include transferring the data unit from the first sublayer to the second sublayer.