Patents Examined by Steven Loke
  • Patent number: 10283640
    Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Sameer S. Pradhan, Subhash M. Joshi, Jin-Sung Chun
  • Patent number: 10256171
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Elbert Huang, Son Nguyen, Takeshi Nogami, Christopher J. Penny, Deepika Priyadarshini
  • Patent number: 10243167
    Abstract: A an organic light-emitting display apparatus, including a first substrate, a display unit having a plurality of organic light-emitting devices that is formed on the first substrate, a second substrate disposed on the display unit, and a filler included between the first substrate and the second substrate. The organic light-emitting device includes a first electrode formed on the first substrate, an intermediate layer that is disposed on the first electrode and includes an organic emission layer, and a porous second electrode disposed on the intermediate layer.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: March 26, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Tae-Wook Kang
  • Patent number: 10217659
    Abstract: A method of making a dual isolation fin comprises applying a mask to a substrate and etching the exposed areas of the substrate to form a mandrel; forming a dielectric layer on the surface of the substrate and adjacent to the mandrel; forming a first epitaxially formed material on the exposed portions of the mandrel; forming a second epitaxially formed material on the first epitaxially formed material; forming a first isolation layer on the dielectric layer and adjacent to the second epitaxially formed material; removing the mask and mandrel after forming the first isolation layer; removing the first epitaxially formed material after removing the mask and mandrel; and forming a second isolation layer.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Sanghoon Lee, Effendi Leobandung
  • Patent number: 10217781
    Abstract: A tunneling field effect transistor for light detection, including a p-type region connected to a source terminal, a n-type region connected to a drain terminal, an intrinsic region located between the p-type region and the n-type region to form a P-I junction or an N-I junction with the n-type region or the p-type region, respectively, a first insulating layer and a first gate electrode, the first gate electrode covering a portion of the intrinsic region on one side, and a second insulating layer and a second gate electrode, the second insulating layer and the second gate electrode covering an entire other side of the intrinsic region opposite to the one side, wherein an area of the intrinsic region that is not covered by the first gate electrode forms a non-gated intrinsic area configured for light absorption.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: February 26, 2019
    Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
    Inventors: Mihai Adrian Ionescu, Nilay Dagtekin
  • Patent number: 10211423
    Abstract: A an organic light-emitting display apparatus, including a first substrate, a display unit having a plurality of organic light-emitting devices that is formed on the first substrate, a second substrate disposed on the display unit, and a filler included between the first substrate and the second substrate. The organic light-emitting device includes a first electrode formed on the first substrate, an intermediate layer that is disposed on the first electrode and includes an organic emission layer, and a porous second electrode disposed on the intermediate layer.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: February 19, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Tae-Wook Kang
  • Patent number: 10197868
    Abstract: A display device includes a first substrate having a first lower column spacer disposed in a peripheral area, extending in a direction, and including first and second opposing slanted sides, a second substrate opposing the first substrate, the second substrate including a first upper column spacer disposed in the first peripheral area, extending in the same direction, including a slanted side, and disposed adjacent to the first side of the first lower column spacer, and a second upper column spacer having substantially a same shape as the first upper column spacer and disposed adjacent to the second side of the first lower column spacer, where the first peripheral area is disposed outside a display area of the display device.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae Hoon Jung, Hyangyul Kim, Hyoung-Joon Kim
  • Patent number: 10199278
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate, wherein a hardmask is formed on each of the plurality of fins, forming a gate structure around the plurality of fins, selectively depositing a dummy dielectric on the hardmask on each of the plurality of fins, depositing a dielectric layer on the gate structure and around the dummy dielectrics, selectively removing the dummy dielectrics and the hardmasks with respect to the dielectric layer and the gate structure to create a plurality of openings exposing portions of the gate structure, and selectively removing the exposed portions of the gate structure through the plurality of the openings.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: February 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10199566
    Abstract: A semiconductor device includes a magnetic tunnel junction structure on a lower electrode, an intermediate electrode on the magnetic tunnel junction structure, and an upper electrode on the intermediate electrode, wherein the intermediate electrode includes a lower portion and an upper portion having a side surface profile different from that of the lower portion.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Ik Oh, Jong-Kyu Kim, Jongchul Park, Gwang-Hyun Baek, Kyungrae Byun, Hyun-Woo Yang
  • Patent number: 10192833
    Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: January 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Wei Kuo, Hui Yu Lee, Huan-Neng Chen, Yen-Jen Chen, Yu-Ling Lin, Chewn-Pu Jou
  • Patent number: 10177190
    Abstract: A photoelectric conversion portion, a charge holding portion, a transfer portion, and a sense node are formed in a P-type well. The charge holding portion is configured to include an N-type semiconductor region, which is a first semiconductor region holding charges in a portion different from the photoelectric conversion portion. A P-type semiconductor region having a higher concentration than the P-type well is disposed under the N-type semiconductor region.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: January 8, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yusuke Onuki, Yuichiro Yamashita, Masahiro Kobayashi
  • Patent number: 10173889
    Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a wiring layer and substrate. The method further includes forming an insulator layer over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity of the MEMS.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: January 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Russell T. Herrin, Christopher V. Jahnes, Anthony K. Stamper, Eric J. White
  • Patent number: 10177076
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Elbert Huang, Son Nguyen, Takeshi Nogami, Christopher J. Penny, Deepika Priyadarshini
  • Patent number: 10170690
    Abstract: A magnetic memory device and a method to make the device is disclosed. The magnetic memory device comprises a free magnetic layer that includes a hard magnetic material layer, a soft magnetic material layer and a coupling layer that is between the hard magnetic material layer and the soft magnetic material layer. The coupling layer comprises a magnetic material that has oxidized edges. In one embodiment, the magnetic material of the coupling layer comprises a Heusler alloy or a silicon-based magnetic material. A predetermined amount of the coupling layer is oxidized to controllably reduce the switching current Jc0 of the free magnetic layer to be about half of the switching current if the coupling layer comprised substantially all magnetic material and no oxide.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: January 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dmytro Apalkov, Donkoun Lee, Mohamad Krounbi
  • Patent number: 10164161
    Abstract: A light emitting arrangement is suggested for generating directional projections of light with sharply defined beam profile. Light from a top-emitting solid state light source (12), having reflective side-coating (34), is pre-collimated via a beam-shaping optic (16), before being propagated through a secondary collimating funnel (18), capturing any light rays with still too great an escape angle. Chip-scale package dimensions may be achieved through the use of a thin-film side-coating and undersized phosphor layers. Substrate level process flow further allows for parallel processing of a plurality of devices.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: December 25, 2018
    Assignee: Koninklijke Philips N.V.
    Inventors: Norbertus Antonius Maria Sweegers, Floris Maria Hermansz Crompvoets, Marc Andre De Samber
  • Patent number: 10163744
    Abstract: A semiconductor device has a substrate including a recess and a peripheral portion with through conductive vias. A first semiconductor die is mounted over the substrate and within the recess. A planar heat spreader is mounted over the substrate and over the first semiconductor die. The planar heat spreader has openings around a center portion of the planar heat spreader and aligned over the peripheral portion of the substrate. A second semiconductor die is mounted over the center portion of the planar heat spreader. A third semiconductor die is mounted over the second semiconductor die. First and second pluralities of bond wires extend from the second and third semiconductor die, respectively, through the openings in the planar heat spreader to electrically connect to the through conductive vias. An encapsulant is deposited over the substrate and around the planar heat spreader.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: December 25, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: OhHan Kim, WonJun Ko, DaeSik Choi
  • Patent number: 10163952
    Abstract: A method for forming a backside illuminated (BSI) image sensor device structure is provided. The BSI image sensor includes a first substrate having a top surface and a bottom surface, and a plurality of pixel regions formed at the top surface of the first substrate. The BSI image sensor also includes a grid structure through the first substrate and between two adjacent pixel regions. The grid structure extends continuously through the first substrate in a vertical direction and has a top surface and a bottom surface, the top surface of the grid structure protrudes above the bottom surface of the first substrate, and the bottom surface is leveled with the top surface of the first substrate.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Chan Chen, Yueh-Chuan Lee, Chih-Huang Li, Ta-Hsin Chen
  • Patent number: 10163956
    Abstract: An apparatus comprises a first semiconductor chip including a first substrate, a plurality of first inter-metal dielectric layers and a plurality of first metal lines, a second semiconductor chip having a surface in contact with a surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second inter-metal dielectric layers and a plurality of second metal lines and a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion over a first side of a hard mask layer and a second portion over a second side of the hard mask layer, wherein the hard mask layer is a ring-shaped layer, and wherein the conductive plug is formed in a center opening of the ring-shaped layer.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Shih Pei Chou, Min-Feng Kao, Szu-Ying Chen
  • Patent number: 10163870
    Abstract: Disclosed herein is a light emitting device package and a light emitting device package module.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: December 25, 2018
    Assignee: LUMENS CO., LTD.
    Inventors: Hyo Gu Jeon, Jung Hyun Park, Dae Gil Jung, Seung Hyun Oh, Yun Geon Cho, Bo Gyun Kim, Suk Min Han, Jun Hyeok Han
  • Patent number: 10158050
    Abstract: A light-emitting diode package includes a frame portion with a chip-mounting region defined in an upper portion thereof, and first and second frames spaced apart from each other. A light-emitting diode is mounted on at least a portion of the chip-mounting region with a bonding layer interposed therebetween. The frame portion includes a depressed portion formed on an upper surface thereof, and the depressed portion includes the chip-mounting region defined on a bottom thereof. The depressed portion also includes a step portion disposed at an outer upper end thereof.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: December 18, 2018
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jun Yong Park, Hee Cheul Jung, In Kyu Park, Daewoong Suh