Abstract: Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.

Abstract: A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 1×1017 cm?3, extending from the p-type layer through the n-type layer to the n-type substrate. The low dynamic resistance, low capacitance diode also includes an n-type region disposed in the p-type layer, extending to a top surface of the p-type layer.

Abstract: A display substrate, a method of manufacturing the same, and a display device including the display substrate disclosed. In one aspect, the display substrate includes a pixel circuit disposed over a base substrate, an insulation layer disposed over the base substrate and overlapping the pixel circuit in the depth dimension of the display substrate, and a pixel electrode disposed over the insulation layer and electrically connected to the pixel circuit. The display substrate also includes a pixel defining layer disposed over the insulation layer, the pixel defining layer formed over a portion of the pixel electrode, and a spacer structure including a first spacer and a second spacer disposed over the first spacer, the first spacer being separated from the pixel circuit and disposed over the insulation layer.

Abstract: A semiconductor device includes a base including a substrate and a first insulating layer formed thereon. The base has a first surface and a second surface that is opposite to the first surface, and has an opening that passes through from the first surface to the second surface. A first width of the opening at the first surface is greater than a second width of the opening at the second surface. An electrode formed on the second surface of the base and covers the opening. A metal layer fills the opening and is electrically connected to the electrode.

Abstract: Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the semiconductor devices includes a substrate, a gate stack over the substrate and a strained layer in a recess of the substrate and aside the gate stack. Besides, a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7.

Abstract: A field effect transistor (FET) includes a gate dielectric layer, a two-dimensional (2D) channel layer formed on the gate dielectric layer and a gate electrode. The 2D channel layer includes a body region having a first side and a second side opposite to the first side, the body region being a channel of the FET. The 2D channel layer further includes first finger regions each protruding from the first side of the body region and second finger regions each protruding from the second side of the body region. A source electrode covers the first finger regions, and a drain electrode covers the second finger regions.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the substrate; forming a thyristor on the cell region; removing the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer on the peripheral region; and forming a metal oxide semiconductor (MOS) transistor on the peripheral region.

Abstract: Provided is a light emitting semiconductor device comprising a flexible dielectric layer, a conductive layer on at least one side of the dielectric layer, at least one cavity or via in the dielectric substrate, and a light emitting semiconductor supported by the cavity or via. Also provided is a support article comprising a flexible dielectric layer, a conductive layer on at least one side and at least one cavity or via in the dielectric substrate. Further provided is a flexible light emitting semiconductor device system comprising the above-described light emitting semiconductor device attached to the above-described support article.

Abstract: A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the channel material is different from the lattice constant of the bulk substrate to introduce strain to the channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate.

Abstract: An active device array substrate including a first scan line, a first data line, a second data line, a first active device, a first pixel electrode, a second active device, a second pixel electrode, and a first shielding pattern layer is provided. The first active device includes a first gate electrically connected to the first scan line, a first semiconductor pattern layer, a first source electrically connected to the first data line, and a first drain. The second active device includes a second gate electrically connected to the first scan line, a second semiconductor pattern layer, a second source electrically connected to the second data line, and a second drain. The first shielding pattern layer is overlapped with the first semiconductor pattern layer and the second semiconductor pattern layer. The first shielding pattern layer is overlapped with the second data line and not overlapped with the first data line.

Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

Abstract: A system, method, and apparatus for an avalanche photodiode with an enhanced multiplier layer are disclosed herein. In particular, the present disclosure teaches an avalanche photodiode having a multiplier with alternating layers of one or more quantum wells and one or more spacers. A method of making the avalanche photodiode includes growing the multiplier on a substrate.

Abstract: A silicon controlled rectifier including a semiconductor substrate, first and second semiconductor wells, first and second semiconductor regions, third and fourth semiconductor regions and a silicide layer is provided. The first and the second semiconductor wells are formed in the semiconductor substrate. The first and the second semiconductor regions are respectively formed in the first and the second semiconductor wells in spaced apart relation. The third and the fourth semiconductor regions are respectively formed in the first and the second semiconductor wells. The silicide layer is formed on the third and the fourth semiconductor regions. The silicon controlled rectifier is at least suitable for high frequency circuit application. The silicon controlled rectifier has a relatively low trigger voltage, a relatively high electrostatic discharge level, and a relatively low capacitance.

Abstract: Embodiments of the present disclosure relate to a cooler for semiconductor devices. The semiconductor device may be electrically coupleable to a power source. The device may generate heat when the power source supplies power to the device during use of the device. The cooler may be coupled to one or more surfaces of the device. The cooler may include a hydrophilic material to adsorb water from ambient air. During operation of the device, the cooler may cool the device by conduction of heat away from the device to the cooler. The cooler may include water that is evaporated during use of the device to increase cooling capacity of the cooler. The cooler may be recharged with water from humidity in air when the device is not operated or operated at a lower power level. Other embodiments may be described and/or claimed.

Abstract: A semiconductor device has a semiconductor wafer and a conductive via formed through the semiconductor wafer. A portion of the semiconductor wafer is removed such that a portion of the conductive via extends above the semiconductor wafer. A first insulating layer is formed over the conductive via and semiconductor wafer. A second insulating layer is formed over the first insulating layer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. A portion of the first and second insulating layers is removed simultaneously from over the conductive via by chemical mechanical polishing (CMP). Alternatively, a first insulating layer including an organic material is formed over the conductive via and semiconductor wafer. A portion of the first insulating layer is removed by CMP. A conductive layer is formed over the conductive via and first insulating layer. The conductive layer is substantially planar.

Abstract: A FinFET including a substrate, a plurality of insulators and a gate stack is provided. The substrate comprises a plurality of trenches and at least one semiconductor fin between the trenches, wherein the semiconductor fin comprises at least one groove, and the at least one groove is located on a top surface of the semiconductor fin. The insulators are disposed in the trenches. The gate stack partially covers the semiconductor fin, the at least one groove and the insulators.

Abstract: The present invention provides a semiconductor structure including a substrate defining a memory cell region and a peripheral region, a periphery gate stacking structure located within the peripheral region, wherein the periphery gate stacking structure includes at least a first gate layer, and a second gate layer disposed on the first gate layer. The semiconductor structure further includes a cell stacking structure located within the memory cell region, the cell stacking structure having at least a first insulating layer partially disposed in the substrate, a top surface of the first insulating layer being higher than a top surface of the substrate, and the top surface of the first insulating layer and a top surface of the first gate layer being on a same level.

Abstract: An electric static discharge (ESD) diode pair is disclosed. The first diode of the device includes a first diode junction portion having vertically orientated and horizontally oriented portions of a first conductivity and a second diode junction portion of a second conductivity in direct contact with both of the vertically orientated and horizontally orientated portions of the first diode junction portion. The second diode of the device includes a first diode junction portion having vertically orientated and horizontally oriented portions of a second conductivity and a second diode junction portion having a first conductivity in direct contact with both of the vertically orientated and horizontally orientated portions of the first diode junction portion. A common electrical contact is in direct contact first diode junction portion for each of the first diode and the second diode.

Abstract: A semiconductor device includes trench structures that extend from a first surface into a semiconductor body. The trench structures include a gate structure and a contact structure that extends through the gate structure, respectively. Transistor mesas are between the trench structures. Each transistor mesa includes a body zone forming a first pn junction with a drift structure and a second pn junction with a source zone. Diode regions directly adjoin one of the contact structures form a third pn junction with the drift structure, respectively.

Abstract: Systems and methods of manufacturing compact camera assemblies for use in electronic device are provided. The camera assemblies include an image sensor and a camera component. The camera assemblies further include a molding compound transfer molded onto the image sensor and the camera component to form a camera component subassembly. A redistribution layer is formed on a surface of the camera component subassembly. The redistribution layer includes at least one dielectric layer and a first interconnect layer. The camera assemblies further include a lens module coupled to the redistribution layer and aligned with the image sensor along an optical axis.