Abstract: A package structure and packing method for an organic electroluminescence element and an organic electroluminescence device are provided. The package structure for the organic electroluminescence element includes: a substrate, an organic electroluminescence element, and a quantum dot packaging layer. The organic electroluminescence element is disposed on the substrate, the quantum dot packaging layer is disposed on the substrate and the organic electroluminescence element, and consists of a quantum dot material.

Abstract: A flexible display device of which esthetic appearance is improved by reducing a bezel is disclosed. The flexible display device comprises a substrate including a display area and a non-display area including a bending area; a link line in the non-display area on the substrate; and a bending connection line in the bending area of the substrate and connected with the link line, and the bending connection line located between a first buffer layer and a second buffer layer of the flexible display device.

Abstract: A display device includes a flexible display panel and a protective film. The protective film includes a film main body and a first adhesion portion. The film main body has a first surface contacting the flexible display panel and a first recess portion recessed from the first surface, and the first adhesion portion is in the first recess portion.

Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

Abstract: A light emitting diode including a first conductive type semiconductor layer, a mesa disposed on the first conductive type semiconductor layer, the mesa including an active layer and a second conductive type semiconductor layer, a reflective electrode disposed on the mesa and configured to be in ohmic-contact with the second conductive type semiconductor layer, a current spreading layer disposed on the mesa and the reflective electrode, the current spreading layer including a first portion configured to be in ohmic-contact with an upper surface of the first conductive type semiconductor layer, a first n-contact region spaced apart from a second n-contact region with the mesa disposed between the first and second n-contact regions, and an insulation layer including a first opening exposing the reflective electrode between the first and second n-contact regions. The first and second n-contact regions have a second opening that exposes the first conductive type semiconductor layer.

Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

Abstract: The present disclosure provides a package structure of an organic light emitting component and a method for manufacturing the same. The package structure includes: a substrate, provided with light emitting pixels; a first barrier layer, arranged on the substrate; a nanoparticle layer, arranged on a portion of the first barrier layer corresponding to a location of the light emitting pixels, wherein the nanoparticle layer is configured to extract light from the light emitting pixels; a buffer layer, arranged on another portion of the first barrier layer where the nanoparticle layer is not set; a second barrier layer, arranged on the nanoparticle layer and the buffer layer. The implementation of the present disclosure allows the light extraction to be applied only on the light emitting pixels. Therefore, it can avoid the waste of material and reduce production cost.

Abstract: Related to is the field of light-emitting panel manufacture, and a light-emitting panel and a method for manufacturing the same are provided, which aim to improve uniformity of light emission of an Organic Light-Emitting Diode (OLED) manufactured by Inkjet Printing (IJP). The light-emitting panel sequentially comprises an ITO substrate, a light-emitting layer, a light-shielding layer, and a cover glass. The method comprises forming a multilayer structure sequentially including an ITO substrate, a light-emitting layer, a light-shielding layer, and a cover glass. According to a size of an edge warp of a light-emitting area of the OLED, a light-shielding layer is designed at a corresponding position of the light-emitting area on the cover glass, and a position of a non-uniform edge is subjected to light-shielding processing, so that the problem of non-uniform light emission caused by the edge warp of the organic light-emitting layer is solved.

Abstract: The present disclosure provides an OLED array substrate comprising a plurality of pixel units each including a plurality of sub-pixel units, each of the sub-pixel units comprising a light-emitting portion, each light-emitting portion having a first electrode, a second electrode and an organic light-emitting layer sandwiched between the first electrode and the second electrode, wherein the sub-pixel unit further comprises an organic film layer and a semi-reflecting mirror layer disposed successively on a light exit side of the second electrode, the first electrode comprises a reflective layer, the second electrode is a transparent electrode, a structure between the first electrode and the semi-reflecting mirror layer constitutes a microcavity structure, and organic film layers of the sub-pixel units of different colors of each pixel unit have different thicknesses. The present disclosure further provides an OLED display panel, an OLED display device, and a method of manufacturing the array substrate.

Abstract: A semiconductor device includes a drift layer, a base layer, a collector layer, gate insulating films, gate electrodes, an emitter region, a first electrode and a second electrode. The base layer is provided on the drift layer. The drift layer is provided between the base layer and the collector layer. The gate insulating films are respectively provided on wall surfaces of trenches penetrating the base layer to reach the drift layer. The gate electrodes are respectively provided on the gate insulating films. The emitter region is provided in a surface layer portion of the base layer, and is in contact with the trenches. The first electrode is electrically coupled with the base layer and the emitter region. The second electrode is electrically coupled with the collector layer. Some gate electrodes are applied with a gate voltage. Other gate electrodes are electrically coupled to the first electrode.

Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.

Abstract: A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector. A recess extends from the top surface of the molding compound into the molding compound.

Abstract: A semiconductor structure is provided, which includes a semiconductor device, a first conductive layer, and a gate runner. The semiconductor device includes an upper surface, a gate terminal, a source terminal, and a drain terminal. The first conductive layer is deposited on the upper surface and coupled to the source terminal. The gate runner is overlapped with the first conductive layer and coupled to the gate terminal. The gate runner and the first conductive layer are configured to contribute a parasitic capacitance between the gate terminal and the source terminal.

Abstract: An electronic device including: a substrate; a first electrically-conductive layer; a second electrically-conductive layer; and an intermediate layer. The first electrically-conductive layer is disposed on the substrate and composed of aluminum or an aluminum alloy. The second electrically-conductive layer is spaced away from the first electrically-conductive layer. The intermediate layer is disposed between the first electrically-conductive layer and the second electrically-conductive layer, is in contact with both the first electrically-conductive layer and the second electrically-conductive layer, and contains aluminum and fluorine.

Abstract: The present invention provides a metal-oxide-metal (MOM) capacitor including a first metal layer and a second metal layer. The first metal layer includes a plurality of first metal stripes and second metal stripes extending along a first direction and a plurality of first metal jogs and second metal jogs extending along a second direction. Each of the first metal jogs is connected to one of the first metal stripes and each of the second metal jogs is connected to one of the second metal stripes. The second metal layer includes a plurality of third metal stripes and fourth metal stripes extending along the first direction and includes a plurality of third metal jogs and fourth metal jogs. Each of the third metal jogs is connected to one of the third metal stripes and each of the fourth metal jogs is connected to one of the fourth metal stripes.

Abstract: A semiconductor structure includes a semiconductor substrate, n-type source and drain stressors, and a gate stack. The semiconductor substrate has source and drain recesses therein. The n-type source and drain stressors are respectively present in the source and drain recesses. At least one of the n-type source and drain stressors has a hydrogen terminated surface. A gate stack is present on the semiconductor substrate and between the n-type source and drain stressors.

Abstract: A method of determining a chromaticity rank of a light emitting device includes selecting the light emitting device having a chromaticity rank in a region surrounded by four defining points on a 1931 CIE Chromaticity Diagram. A ratio of a distance in a y-direction between, of the four defining points, two defining points furthest from each other in the y-direction to a distance in an x-direction between, of the four defining points, two defining points furthest from each other in the x-direction is 0.5 or less A peak light emission wavelength of the blue light emitting element is in a range of 447 to 452 nm, a peak light emission wavelength of the green light emitting element is in a range of 520 to 541 nm, and a peak light emission wavelength of the red light emitting element is in a range of 630 to 632 nm.

Abstract: The present disclosure discloses an OLED display panel, including a TFT array substrate and a plurality of anodes disposed in an array on the TFT array substrate, the TFT array substrate has a pixel defining layer disposed thereon, the pixel defining layer includes opening portions and spacing portions, and each opening portion corresponds to one sub-pixel area; wherein, the pixel defining layer has a first common layer, a second common layer and a cathode layer sequentially disposed thereon, and a light emitting material is disposed between the first common layer and the second common layer corresponding to each sub-pixel area; wherein, a hole blocking portion is further disposed above the spacing portion, and the hole blocking portion spaces the first common layer between two adjacent sub-pixel areas. The present disclosure further discloses a method for manufacturing the OLED display panel as mentioned above.

Abstract: A light-emitting device includes a light-emitting element disposed on a mount substrate, a reflective member disposed around the light-emitting element to cover the light-emitting element, and a dam disposed on opposite sides of the reflective member. The dam includes a resin dam, and a surface layer covering at least part of a surface of the resin dam. The inner lateral surface of the resin dam facing the light-emitting element is covered with the surface layer, and at least part of the outer lateral surface of the resin dam not facing the light-emitting element is an exposed surface.

Abstract: A semiconductor device includes a substrate, a source region and a drain region, a gate dielectric layer, and a ferroelectric material layer. The ferroelectric material layer overlaps with the source region and overlaps with the drain region. The substrate further comprises a channel layer. A gate electrode is disposed on the substrate. The ferroelectric material layer is disposed between the channel layer and the gate electrode.