Patents Examined by Suberr L Chi
  • Electric component with sensitive component structures and method for producing an electric component with sensitive component structures
    Patent number: 11245977
    Abstract: The invention relates to a simple to produce electric component for chips with sensitive component structures. Said component comprises a connection structure and a switching structure on the underside of the chip and a support substrate with at least one polymer layer.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: February 8, 2022
    Assignee: Snaptrack, Inc.
    Inventors: Christian Bauer, Hans Krüger, Jürgen Portmann, Alois Stelzl, Wolfgang Pahl
  • Light emitting diode constructions and methods for making the same
    Patent number: 11245058
    Abstract: Light emitting diode (LED) constructions comprise an LED having a pair of electrical contacts along a bottom surface. A lens is disposed over the LED and covers a portion of the LED bottom surface. A pair of electrical terminals is connected with respective LED contacts, are sized larger than the contacts, and connect with the lens material along the LED bottom surface. A wavelength converting material may be interposed between the LED and the lens. LED constructions may comprise a number of LEDs, where the light emitted by each LED differs from one another by about 2.5 nm or less. LED constructions are made by attaching 2 or more LEDs to a common wafer by adhesive layer, forming a lens on a wafer level over each LED to provide a rigid structure, removing the common wafer, forming the electrical contacts on a wafer level, and then separating the LEDs.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: February 8, 2022
    Assignee: Bridgelux, Inc.
    Inventors: Vladimir A. Odnoblyudov, R. Scott West
  • Asymmetric FET for FDSOI devices
    Patent number: 11245032
    Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: February 8, 2022
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Ignasi Cortes, Alban Zaka, Tom Herrmann, El Mehdi Bazizi, Richard Francis Taylor, III
  • Photoelectric conversion device, substrate, and system with semiconductor regions
    Patent number: 11239380
    Abstract: Photoelectric conversion device includes semiconductor chip including first semiconductor region, second semiconductor region arranged on the first semiconductor region, and third semiconductor region arranged on the second semiconductor region. Chip end face of the semiconductor chip is formed by the first semiconductor region, the second semiconductor region and the third semiconductor region. The first semiconductor region is of first conductivity type and the second semiconductor region is of second conductivity type. The third semiconductor region includes photoelectric conversion region, readout circuit region, and peripheral region. The peripheral region includes isolation region and outer periphery region arranged between the chip end face and the isolation region. The isolation region is of the second conductivity type and the outer periphery region is of the first conductivity type.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: February 1, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yuuichirou Hatano, Takahiro Shirai
  • Ultraviolet c light-emitting diode
    Patent number: 11233173
    Abstract: An ultraviolet C light-emitting diode including an n-type semiconductor layer, a p-type semiconductor layer, an active layer, a two-dimensional hole gas (2DHG) inducing layer, and an electron blocking layer is provided. The active layer is disposed between the n-type semiconductor layer and the p-type semiconductor layer, wherein a wavelength of a maximum peak of a spectrum emitted by the active layer ranges from 230 nm to 280 nm. The two-dimensional hole gas (2DHG) inducing layer is disposed between the active layer and the p-type semiconductor layer. A concentration of magnesium in the 2DHG inducing layer is less than 1017 atoms/cm3. The electron blocking layer is disposed between the p-type semiconductor layer and the 2DHG inducing layer. A concentration of magnesium in a part of the electron blocking layer adjacent to the 2DHG inducing layer is greater than 1019 atoms/cm3.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 25, 2022
    Assignees: Industrial Technology Research Institute, OPTO TECH CORP.
    Inventors: Chia-Lung Tsai, Hsueh-Hsing Liu, Chang Da Tsai
  • Display device having a charge generation layer
    Patent number: 11227905
    Abstract: A display device is disclosed, which is capable of preventing a leakage current between neighboring pixels. The display device includes a substrate including a first sub pixel and a second sub pixel, first electrodes patterned in the respective first and second sub pixel on the substrate, a bankwall provided between the first electrodes, a bank provided to cover an end of the first electrode and configured to expose some portions of the first electrode, an emission layer provided on the bankwall and the bank, and configured to include a first stack, a second stack, and a charge generation layer disposed between the first stack and the second stack, and a second electrode provided on the emission layer, wherein the emission layer includes a disconnected area in which the charge generation layer is disconnectedly provided by the bankwall.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: January 18, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: YoungMi Kim, Wooram Youn
  • Display device with passivation layer that directly contacts the substrate and manufacturing method thereof
    Patent number: 11227873
    Abstract: A display device includes: a substrate; a transistor disposed on a first surface of the substrate; and a passivation layer disposed on a second surface of the substrate opposite from the first surface, wherein the passivation layer directly contacts the substrate, and the passivation layer includes a UV curable resin.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: January 18, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Woo Yong Sung, Doo Hwan Kim
  • Photosensitive element having substantially flat interface between electrode and photosensitive layer and manufacturing method thereof
    Patent number: 11227874
    Abstract: A photosensitive element and a manufacturing method thereof are provided. The manufacturing method of the photosensitive element includes successively depositing a second conductive layer, a photosensitive material layer, and a first top electrode material layer on a substrate; forming a first patterned photoresist layer on the first top electrode material layer; patterning the first top electrode material layer by using the first patterned photoresist layer as a mask to form a first top electrode; removing the first patterned photoresist layer; patterning the photosensitive material layer by using the first top electrode as a mask to form a photosensitive layer; forming an insulation layer having an opening on the first top electrode; and forming a second top electrode on the insulation layer, and the second top electrode is electrically connected to the first top electrode via the opening.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: January 18, 2022
    Assignee: Au Optronics Corporation
    Inventors: Po-Chao Chang, Ruei-Pei Chen, Kuo-Yu Huang, Chao-Chien Chiu
  • Semiconductor device including insulated gate bipolar transistor element and freewheeling diode element
    Patent number: 11217580
    Abstract: A semiconductor device includes a single semiconductor substrate on which an IGBT region including an IGBT element and an FWD region including a FWD element are formed. In the semiconductor device, a cathode layer is formed with a carrier injection layer, which is electrically connected to a second electrode and has a PN junction with a field stop layer. When a first carrier in the FWD element passes through the field stop layer on the carrier injection layer and flows into the cathode layer in a situation where a forward-biased current is cut off from a state in which the forward-biased current is flowing through the FWD element, a second carrier is injected from the second electrode into a drift layer through the carrier injection layer.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: January 4, 2022
    Assignee: DENSO CORPORATION
    Inventor: Taku Mizukami
  • Device and method for temperature monitoring of a semiconductor device
    Patent number: 11215513
    Abstract: A semiconductor device includes a plurality of active area structures. One or more active devices include portions of the plurality of active area structures. A metal layer is formed on the plurality of active area structures and separated from the one or more active devices by one or more dummy gate layers. The metal layer is configured to measure, due to a change of resistance in the metal layer, a temperature of the plurality of active area structures.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Zeng Kang, Wen-Shen Chou, Yung-Chow Peng
  • Semiconductor device with capacitor contact surrounded by conductive ring and manufacturing method of the semiconductor device
    Patent number: 11217587
    Abstract: A semiconductor device and a manufacturing method are provided. The semiconductor device includes an active region, a bit line, a capacitor contact, a conductive ring and a storage capacitor. The active region is formed in a substrate. The bit line and the capacitor contact are disposed over the substrate and electrically connected with the active region. The bit line is laterally separated from the capacitor contact, and a top surface of the bit line is lower than a top surface of the capacitor contact. An upper portion of the capacitor contact is surrounded by the conductive ring. The storage capacitor is disposed over and in electrical contact with the capacitor contact and the conductive ring.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: January 4, 2022
    Assignee: Winbond Electronics Corp.
    Inventor: Noriaki Ikeda
  • Semiconductor memory structure having drain stressor, source stressor and buried gate and method of manufacturing the same
    Patent number: 11211491
    Abstract: The present disclosure provides a semiconductor memory structure and a method for preparing the semiconductor memory structure. The semiconductor memory structure includes a substrate, a gate structure, a drain stressor and a source stressor. The gate structure is disposed in the substrate. Each of the source stressor and the drain stressor includes a strained part disposed in the substrate.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 28, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Cheng-Hsiang Fan
  • Dummy structure at fin cut
    Patent number: 11205714
    Abstract: In one example, a semiconductor device includes a substrate, a first elongated fin structure disposed on the substrate, and a second elongated fin structure disposed on the substrate. The longitudinal axis of the first elongated fin structure is aligned with a longitudinal axis of the second elongated fin structure. The device further includes a dummy structure extending between the first elongated fin structure and the second elongated fin structure. The dummy structure includes a dielectric material.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: December 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Chih-Hao Wang
  • Semiconductor device with isolation layer and fabrication method thereof
    Patent number: 11205721
    Abstract: A semiconductor device and its fabrication method are provided. The method includes providing a base substrate; forming a first well region and a second well region in the base substrate; forming a gate electrode structure, sidewall spacers, a doped source layer, a doped drain layer and a dielectric layer over the base substrate, where the doped source layer and the doped drain layer are respectively on two sides of the gate electrode structure and the sidewall spacers, and the gate electrode structure and the sidewall spacers are over the first well region and the second well region; removing a portion of the gate electrode structure on the second well region and a portion of the base substrate of the second well region to form a trench in the dielectric layer, where the trench exposes a portion of the sidewall spacers; and forming an isolation layer in the trench.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 21, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Low onset gain saturation OLED
    Patent number: 11201314
    Abstract: Embodiments of this invention relate to and, more particularly, to solid state lighting, digital displays, conversion of electrical energy to light, low onset gain saturated stimulate emission, light production with high efficiency and high output per area, and light production while limiting material degradation, and may also be applied in optical or quantum information processing and networking. Embodimenta of this invention comprise spectroscopic configurations having a radiative transition to a depopulated state and an optical configuration having sufficient Q such that the combination allows onset of gain saturation with a small excited state population or low current density, thus enabling production of light in a mode with near total output coupling, high efficiency, high output, low roll-off and attenuation of losses and degradation processes.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 14, 2021
    Inventor: Mitchell C. Nelson
  • Display device including a trench and manufacturing method thereof
    Patent number: 11201197
    Abstract: A display device includes: a substrate; a plurality of pixels on the substrate; an insulating film on the substrate; a bank on the insulating film, wherein the bank partitions the plurality of pixels; a first trench in the bank; and a second trench in the insulating film. A method of manufacturing a display device includes: forming a first lower metal layer and a second metal layer in patterns on a substrate; forming a first insulating film on the first lower metal layer and the second lower metal layer; forming a second insulating film on the first insulating film; forming a first trench to expose the second lower metal layer by performing a first etching process; and forming a second trench by performing a second etching process to etch the second lower metal layer exposed from a bottom of the first trench.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: December 14, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Hyeong-Jun Lim, Doo-Hyn Yoon, Han-Sun Park
  • Display apparatus having zero bezel by bending bezel area
    Patent number: 11189670
    Abstract: Currently described is a display that has a base layer, and on top of that base layer is a buffer layer with two exposed portions. The exposed portions are covered with a film. A pixel layer is placed between the two films, and a first substrate is attached to the pixel layer using an adhesive layer. The substrate is designed using either multiple thicknesses or grooves to facilitate a curvature radius of the end portions of the display to achieve a zero bezel display.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: November 30, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Moonsun Lee, Eunah Kim
  • Display panel with insulating stripes in non-display area and method of fabricating thereof
    Patent number: 11183520
    Abstract: The present application provides a display panel and a method of fabricating the same. The display panel includes a display area, a non-display area, and a channel. The non-display area includes a first insulating layer, a second insulating layer, a first conductive layer, and a third insulating layer. The surface of the second insulating layer has a plurality of convex portions and a plurality of concave portions that are continuously distributed. The first conductive layer covers the second insulating layer. The third insulating layer includes a plurality of insulating strips spaced apart on the first conductive layer, and the plurality of insulating strips are disposed corresponding to the plurality of concave portions.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: November 23, 2021
    Inventors: He Jiang, Kotaro Yoneda
  • Semiconductor packages and associated methods with antennas and EMI isolation shields
    Patent number: 11177222
    Abstract: Semiconductor devices with antennas and electromagnetic interference (EMI) shielding, and associated systems and methods, are described herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a package substrate. An antenna structure is disposed over and/or adjacent the semiconductor die. An electromagnetic interference (EMI) shield is disposed between the semiconductor die and the antenna structure to shield at least the semiconductor die from electromagnetic radiation generated by the antenna structure and/or to shield the antenna structure from interference generated by the semiconductor die. A first dielectric material and/or a thermal interface material can be positioned between the semiconductor die and the EMI shield, and a second dielectric material can be positioned between the EMI shield and the antenna structure.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Dong Soon Lim, Randon K. Richards, Aparna U. Limaye
  • Integrated transistors having gate material passing through a pillar of semiconductor material, and methods of forming integrated transistors
    Patent number: 11177389
    Abstract: Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the segments, and a channel region is within the segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Antonino Rigano, Marcello Mariani