Patents Examined by Sue A. Purvis
  • Patent number: 11348935
    Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Ming Wu, Wei Cheng Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai
  • Patent number: 11349015
    Abstract: A semiconductor device includes a conductive feature over a substrate, a ruthenium-containing feature disposed over the conductive feature, and a first barrier layer disposed over the conductive feature and over sidewalls of the ruthenium-containing feature. The semiconductor device also includes a second barrier layer disposed over sidewalls of the first barrier layer, and a third barrier layer disposed over sidewalls of the second barrier layer. The first, second, and third barrier layers include different material compositions.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Yen-Yu Chen
  • Patent number: 11335832
    Abstract: An LED package structure and a carrier thereof are provided. The LED package structure includes a carrier, a plurality of LED chips, and an encapsulating colloid. The carrier includes a substrate, a ring-shaped first wall disposed on the substrate, and a ring-shaped second wall stacked on the first wall. A portion of the substrate surrounded by the first wall is defined as a die-bonding region, and the first wall, the second wall, and the die-bonding region jointly define an accommodating space. The LED chips are mounted on the die-bonding region and are arranged in the accommodating space. The encapsulating colloid is filled within the accommodating space, and the LED chips are embedded in the encapsulating colloid.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: May 17, 2022
    Assignee: KAISTAR LIGHTING(XIAMEN) CO., LTD.
    Inventors: Tian He, Wei-Hong Yang, Jing Chen
  • Patent number: 11322651
    Abstract: A light-emitting element includes a first semiconductor layer, a second semiconductor layer, a light-emitting layer, a first electrode, and a second electrode. The first semiconductor layer includes gallium and nitrogen and is of an n-type. The second semiconductor layer includes gallium and nitrogen and is of a p-type. The light-emitting layer is provided between the first semiconductor layer and the second semiconductor layer. The first electrode is electrically connected to the first semiconductor layer. The second electrode is electrically connected to the second semiconductor layer. The first semiconductor layer includes a first partial region and a first side surface region. The first partial region includes a first surface contacting the first electrode. The first side surface region includes a first side surface crossing a plane perpendicular to a first direction. The first direction is from the second semiconductor layer toward the first semiconductor layer.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: May 3, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Eiji Muramoto, Akinori Kishi
  • Patent number: 11315896
    Abstract: A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Chen-Hua Yu, Sheng-Yu Wu, Yao-Chun Chuang
  • Patent number: 11282970
    Abstract: An apparatus and method for a detector are disclosed. The apparatus disclosed contains a non-absorbing layer shaped as one or more pyramids, one or more collector regions, an absorber layer disposed between the one or more collector regions and the non-absorbing layer, a first electrical contact, and a second electrical contact, wherein the absorber layer is configured to absorb photons of incident light and generate minority electrical carriers and majority electrical carriers, wherein the one or more collector regions are electrically connected with the absorber layer and with the first electrical contact for extracting the minority electrical carriers, and the absorber layer is electrically connected with the one or more collector regions and with the second electrical contact to extract the majority electrical carriers.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: March 22, 2022
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel Yap, Rajesh D. Rajavel, Sarabjit Mehta
  • Patent number: 11257676
    Abstract: A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 22, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hideaki Matsuyama, Shinya Takashima, Katsunori Ueno, Ryo Tanaka, Masaharu Edo, Daisuke Mori, Hirotaka Suda, Hideaki Teranishi, Chizuru Inoue
  • Patent number: 11257981
    Abstract: The present invention seeks to provide cadmium-free quantum dots with a narrow fluorescence FWHM. The quantum dot does not contain cadmium and its fluorescence FWHM is 30 nm or less. The quantum dot is preferably a nanocrystal containing zinc and tellurium or zinc and tellurium and sulfur or zinc and tellurium and selenium and sulfur. Further, the quantum dot preferably has a core-shell structure in which the nanocrystal serves as a core and the surface of the core is coated with a shell.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: February 22, 2022
    Assignee: NS MATERIALS INC.
    Inventors: Kazunori Iida, Emi Tsutsumi, Yuko Ogura, Masanori Tanaka, Soichiro Nikata, Yuka Takamizuma
  • Patent number: 11257838
    Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ronald A. Weimer, Kyu S. Min, Thomas M. Graettinger, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11244857
    Abstract: A semiconductor structure includes a substrate, a gate structure disposed over the substrate, a dielectric material disposed over the substrate and the gate structure, a conductive structure extending within the dielectric material, and a void extending within the dielectric material and disposed over the gate structure.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chih Tsai, Wei Che Hsu, Yu-Chung Yang, Alexander Kalnitsky
  • Patent number: 11189569
    Abstract: Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: November 30, 2021
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Richard T. Schultz, Regina Tien Schmidt, Derek P. Peterson, Te-Hsuan Chen, Elizabeth C. Conrad, Catherina Simona Matheis Ionescu, Chu-Wen Wang
  • Patent number: 11183550
    Abstract: The light-emitting device includes a display unit in which rectangular light-emitting pixels are arranged, and a light-shielding portion that defines a light-emitting region in the display unit and shields light in a region other than the light-emitting region of the display unit, and at least a part of a boundary between the light-emitting region and the light-shielding portion has a curved shape.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: November 23, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takumi Kodama, Takeshi Koshihara
  • Patent number: 11177329
    Abstract: Display structures for controlling viewing angle color shift are described. In various embodiments, polarization sensitive diffusers, independent controlled cathode thicknesses, filtermasks, touch detection layers, and color filters are described.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: November 16, 2021
    Assignee: Apple Inc.
    Inventors: Aleksandr N. Polyakov, Meng-Huan Ho, Yi Huang, Yi Qiao, David S. Hum, Jean-Pierre S. Guillou, Yanming Li, Jun Qi, KiBeom Kim, Kwang Ohk Cheon, Cheng Chen, Rui Liu, ByoungSuk Kim, Ying-Chih Wang, Hung Sheng Lin, Donghee Nam, Tyler R. Kakuda, Takahide Ishii, Yurii Morozov
  • Patent number: 11164964
    Abstract: Provided is a semiconductor device. The device comprises an epitaxial layer that constitutes a part of an active cell region and is doped with impurities of a first conductivity type at a first concentration; a field stop region that is located below the epitaxial layer and doped with impurities of a second conductivity type at a second concentration which are then activated; and a collector region that is located below the field stop region 70 and is doped with impurities of a second conductivity type. The field stop region is formed by repeatedly alternately arranging regions in which the activation of the impurities of the first conductivity type is relatively strong and regions in which the activation of the impurities of the first conductivity type is relatively weak.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: November 2, 2021
    Assignee: HYUNDAI MOBIS CO., LTD.
    Inventors: Ju Hwan Lee, Hyuk Woo
  • Patent number: 11152227
    Abstract: A method includes encapsulating structures disposed on or over a surface of a substrate in an encapsulant. The method also includes separating the encapsulant from the substrate. An apparatus includes a composite film having structures embedded in an encapsulant. The composite film has a surface with a surface roughness of less than one nm. An apparatus includes an encapsulant film having a surface with indentations formed therein. The surface has a surface roughness apart from the indentations of less than one nm.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 19, 2021
    Assignee: Massachusetts Institute of Technology
    Inventors: Richard Swartwout, Farnaz Niroui, Vladimir Bulovic, Jeffrey H. Lang, Joel Jean
  • Patent number: 11145797
    Abstract: Embodiments relate to forming an elastomeric interface layer (elayer) with a flap over multiple light emitting diode (LED) dies by forming materials across multiple LED dies and removing the materials between the LED dies. The formed flap of the elayer provides a large surface area for adhesion between each LED and a pick-up surface. For example, the flap may have a surface area that is larger than the light emitting surface of the LED die, or larger than the surface area of an elastomeric interface layer without the flap. As such, the elayer allows each LED to be picked up by a pick-up surface and placed onto a display substrate including control circuits for sub-pixels of an electronic display. In some embodiments, the LED dies are micro-LED (?LED) dies.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 12, 2021
    Assignee: Facebook Technologies, LLC
    Inventors: Oscar Torrents Abad, Tilman Zehender, Pooya Saketi, Karsten Moh
  • Patent number: 11127859
    Abstract: A semiconductor device includes a channel structure, a dielectric structure, a gate structure, a first conductive structure, and a second conductive structure. The channel structure has a top surface, a bottom surface, and a sidewall extending from the top surface to the bottom surface. The first conductive structure is disposed on the bottom surface of the channel structure and includes a body portion and at least one convex portion, and a top surface of the convex portion is higher than a top surface of the body portion. The second conductive structure is disposed on the top surface of the channel structure and includes a body portion and at least one convex portion, and a bottom surface of the body portion is higher than a bottom surface of the convex portion.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 21, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Patent number: 11114596
    Abstract: A light-emitting device includes: a light-emitting element; a coating member that covers the light-emitting element; and two external connection electrodes exposed form a first surface of the coating member. Each of the external connection electrodes includes an electrode buried in the coating member; and a metal layer formed on the electrode. A surface of each of the metal layers is exposed from the first surface of the coating member. The first surface of the coating member includes a plurality of grooves between the external connection electrodes.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: September 7, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Yoshikazu Matsuda, Ryo Suzuki
  • Patent number: 11114594
    Abstract: A radiation emitting device comprising light scattering particles of different sizes that at least partially surround an emitter, improving the spatial color mixing and color uniformity of the device. Multiple sizes of light scattering particles are dispersed in a medium to at least partially surround a single- or multiple-chip polychromatic emitter package. The different sizes of light scattering particles interact with corresponding wavelength ranges of emitted radiation. Thus, radiation emitted over multiple wavelength ranges or sub-ranges can be efficiently scattered to eliminate (or intentionally create) spatially non-uniform color patterns in the output beam.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: September 7, 2021
    Assignee: CreeLED, Inc.
    Inventor: Arpan Chakraborty
  • Patent number: 11114431
    Abstract: Electrostatic discharge (ESD) protection device is provided. An ESD device includes a substrate having an input region; a plurality of fins on the substrate in the input region; a well region, doped with first-type ions, in the plurality of fins and in the substrate; an epitaxial layer on each fin in the input region; a drain region, doped with second-type ions, in a top portion of each fin and in the epitaxial layer; an extended drain region, doped with the second-type ions, in a bottom portion of each fin to connect to the drain region and in a portion of the substrate, in the input region; and a counter-doped region, doped with the first-type ions, in a portion of the substrate between two adjacent fins to insulate adjacent extended drain regions.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: September 7, 2021
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Yong Li