Abstract: A photoelectric conversion element includes a first electrode, a ferroelectric layer provided on the first electrode, and a second electrode provided on the ferroelectric layer, the second electrode being a transparent electrode, and a pn junction being formed between the ferroelectric layer and the first electrode or the second electrode.

Abstract: A semiconductor device includes a chip body having an uneven surface including at least two regions at different levels from one another, a through electrode penetrating the chip body and having an end which is exposed by the uneven surface of the chip body, a passivation layer disposed on the uneven surface of the chip body, and a bump disposed on the passivation layer and the exposed end of the through electrode and overlapping with the uneven surface of the chip body.

Abstract: A method for chemically passivating a surface of a product made of a III-V semiconductor material in which a) a P(N) polymer film is formed by deposition in a solvent comprising liquid ammonia. The film is formed by deposition, without electrochemical assistance, in the solvent, in the presence of an oxidizing chemical additive comprising phosphorous and generating electrical charge carriers in said surface.

Abstract: The invention concerns a method for producing a transistor. The gate of the transistor is produced after having produced source and drain electrodes of the transistor. From a substrate having a stack of layers comprising at least two surface layers with a first layer of a first semiconductor material intended to produce a conduction channel of the transistor, and a second layer of a second semiconductor material situated on the first layer and intended to at least partly produce the source and drain electrodes of the transistor, the formation of a mask defining a cavity of a gate pattern and the creation of lateral recesses at the periphery of the gate pattern in the second layer and under the mask by an isotropic etching of the second material, and in that it comprises a filling of the lateral recesses with a dielectric material so as to form gate spacers therein.

Abstract: A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.

Abstract: A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional (3D) structure of the diode string.

Abstract: The object to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit is achieved by forming an inverter which comprises: a first transistor including; an first island-shaped semiconductor layer; a first gate insulating film; a gate electrode; a first first-conductive-type high-concentration semiconductor layer arranged above the first island-shaped semiconductor layer; and a second first-conductive-type high-concentration semiconductor layer arranged below the first island-shaped semiconductor layer, and a second transistor including; a second gate insulating film surrounding a part of the periphery of the gate electrode; a second semiconductor layer in contact with a part of the periphery of the second gate insulating film; a first second-conductive-type high-concentration semiconductor layer arranged above the second semiconductor layer; and a second second-conductive-type high-concentration semiconductor layer arranged below the second semiconductor layer.

Abstract: A backside-illuminated photosensor array IC is formed in a thinned circuit wafer. Silicon is removed in at least one substrate-stripped zone where a doped edge-contact ring surrounds the substrate-stripped zone, the edge-contact ring formed in a same first side of the wafer as a plurality of transistors, and opposite to a backside of the wafer. Backside metal is disposed on the backside of the wafer, the backside metal having window openings over the photosensors, and having sidewalls contacting the edge-contact ring around the substrate-stripped zone. The edge contact region is formed in the first side of the device wafer before providing structural support and thinning the device wafer. Substrate-stripped zones, such as bondpad openings and guardring openings, are formed by removing silicon to expose the edge-contact region, and backside metal is deposited with sidewall metal at edges of the substrate-stripped zones and thereby contacting the edge-contact region.

Abstract: An aspect of the invention is a solid-state image capturing device that includes a P-type well 12, an N-type low concentration diffusion layer 18 formed in the P-type well 12, a P-type surface diffusion layer 16 formed on a surface of the N-type low concentration diffusion layer 18, and a P-type high concentration well 15 formed in a boundary region between a side surface of the N-type low concentration diffusion layer 18 and the P-type well 12.

Abstract: An integrated circuit includes a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer, a transistor disposed on the second semiconductor substrate and having a bottom insulated by the insulating layer, a plurality of shallow trench isolations disposed on opposite sides of the transistor, a cavity disposed below the bottom of the transistor, and a plurality of isolation plugs disposed on opposite sides of the cavity. By having a cavity located below the transistor, parasitic couplings between the transistor and the substrate are reduced and the performance of the integrated circuit is improved.

Abstract: In order to increase the spectral response range and improve the mobility of the photo-generated carriers (e.g. in an nBn photodetector), a digital alloy absorber may be employed by embedding one (or fraction thereof) to several monolayers of a semiconductor material (insert layers) periodically into a different host semiconductor material of the absorber layer. The semiconductor material of the insert layer and the host semiconductor materials may have lattice constants that are substantially mismatched. For example, this may performed by periodically embedding monolayers of InSb into an InAsSb host as the absorption region to extend the cutoff wavelength of InAsSb photodetectors, such as InAsSb based nBn devices. The described technique allows for simultaneous control of alloy composition and net strain, which are both key parameters for the photodetector operation.

Abstract: An image sensor is fabricated by forming transfer gates over a substrate layer. A transfer gate is disposed between a respective shared charge-to-voltage conversion region and a photodetector associated with the shared charge-to-voltage conversion region. The transfer gates of each shared charge-to-voltage conversion region are spaced apart to form a conversion region gap. A masking conformal dielectric layer is deposited over the image sensor, covers the transfer gates, fills each conversion region gap, and is etched to form sidewall spacers along an outside edge of each transfer gate with a portion remaining in each conversion region gap and disposed over the substrate layer in each conversion region gap. Source/drain regions are implanted in the substrate layer where an implant region is formed in the transfer gates. The masking conformal dielectric layer in each conversion gap masks the source/drain implant Each charge-to-voltage conversion region is substantially devoid of the implant region.

Abstract: A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ILD) layer insulating adjacent pillar structures; a gate contact penetrating the ILD layer and configured to connect to a sidewall of the gate electrode; and a word line connected to the gate contact.

Abstract: A waveguide-coupled MSM-type photodiode of the present invention comprises a structure in which a semiconductor light-absorbing layer and an optical waveguide core layer are adjacent and optically coupled to each other, has formed metal-semiconductor-metal (MSM) junctions which are arranged at an interval on the semiconductor light-absorbing layer, and is characterized in that of the MSM electrodes arranged at the interval, a voltage is set so that a reverse bias is applied to those MSM electrodes that are arranged on a light incidence side.

Abstract: In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.

Abstract: The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein; a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other; and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings.

Abstract: The present disclosure relates to gate oxide protection circuits, which are used to protect the gate oxides of field effect transistor (FET) elements from over voltage conditions, particularly during situations in which the gate oxides are particularly vulnerable, such as during certain manufacturing stages. Each gate oxide protection circuit may be coupled to a corresponding FET element through corresponding first and second resistive elements, which are coupled to a corresponding gate connection node and a corresponding first connection node, respectively, of the FET element. The gate connection node and the first connection node are electrically adjacent to opposite sides of the gate oxide of the FET element. Each gate oxide protection circuit may protect its corresponding FET element by limiting a voltage between the gate connection node and the first connection node.

Abstract: A basic Spin-Orbit-Torque (SOT) structure with lateral structural asymmetry is provided that produces a new spin-orbit torque, resulting in zero-field current-induced switching of perpendicular magnetization. More complex structures can also be produced incorporating the basic structure of a ferromagnetic layer with a heavy non-magnetic metal layer having strong spin-orbit coupling on one side, and an insulator layer on the other side with a structural mirror asymmetry along the in-plane direction. The lateral structural asymmetry and new spin-orbit torque, in effect, replaces the role of the external in-plane magnetic field. The direction of switching is determined by the combination of the direction of applied current and the direction of symmetry breaking in the device.

Abstract: A silicon carbide single-crystal substrate includes a first surface, a second surface opposite to the first surface, and a peripheral edge portion sandwiched between the first surface and the second surface. A plurality of grinding traces are formed in a surface of the peripheral edge portion. A chamfer width as a distance from an outermost peripheral end portion of the peripheral edge portion to one of the plurality of grinding traces which is located on an innermost peripheral side of the peripheral edge portion in a direction parallel to the first surface is not less than 50 ?m and not more than 400 ?m. Thereby, a silicon carbide single-crystal substrate capable of suppressing occurrence of a crack, and a method for manufacturing the same can be provided.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of dummy gate lines parallel to each other in a first direction and extending in a second direction that is orthogonal to the first direction; a plurality of first dummy filling patterns between the plurality of dummy gate lines, the first dummy filling patterns parallel to each other in the first direction, and arranged apart from each other in the second direction; a plurality of first dummy vias on the plurality of first dummy filling patterns; and a plurality of first dummy wiring lines connected to the plurality of first dummy vias, the first dummy vias extending in the second direction, and parallel to each other in the first direction.