Abstract: A stress mode for use in testing non-volatile memory arrays for a number of types of defects is described. More specifically, a multi-word line select option for a given block can be used for a group of selected word lines to be set to the a programming or other high voltage, while the unselected word lines of the block are set to a pass voltage to minimize electric field differences in order to avoid disturb. For example, a group of selected word lines could number 4, 8 or 16. The multi-word line option can be applied to one block per plane, so that if there are two memory planes, for example, two such blocks can be selected simultaneously for the multi-word line option for those blocks.

Abstract: Provided an electronic device including a semiconductor memory unit. The semiconductor memory unit includes: a plurality of storage cells each including a variable resistance element of which resistance is changed in response to a current flowing across the variable resistance element and a selecting element coupled to one end of the variable resistance element; a plurality of word lines corresponding to the respective storage cells and each coupled to a selecting element of a corresponding storage cell; a first line coupled to one ends of the plurality of storage cells; a second line coupled to the other ends of the plurality of storage cells; a voltage adjuster configured to adjust the voltage levels of back bias voltages of the selecting elements of the plurality of storage cells; and an access control unit electrically coupled to the first and second lines and passing an access current to a selected storage cell among the plurality of storage cells.

Abstract: A semiconductor device includes: a first block, which is initialized during an initialization mode; and a second block, which is initialized while the first block latches first signals during a boot-up mode. Herein, the second block may latch second signals after being initialized during the boot-up mode.

Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method may include determining a performance characteristic using relationship information that relates a bit error rate to at least one of a programming pulse width, a temperature, a history-based predictive performance parameter, a coding scheme, and a voltage level also associated with a memory. The performance characteristic is stored and used to manage a write operation associated with the memory.

Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method may include determining a performance characteristic using relationship information that relates a bit error rate to at least one of a programming pulse width, a temperature, a history-based predictive performance parameter, a coding scheme, and a voltage level also associated with a memory. The performance characteristic is stored and used to manage a write operation associated with the memory.

Abstract: One embodiment provides, in a sense amplifier for an electronic memory array in which a selected memory cell drives a developing voltage differential according to a logic state of the memory cell, a method to store the logic state. The method includes poising source voltages of first and second transistors at levels offset, respectively, by threshold voltages of the first and second transistors. The method also includes applying the voltage differential between a gate of the first transistor and a gate of the second transistor, the first and second transistors configured to oppose each other in a cross-coupled inverter stage of the sense amplifier.

Abstract: A DRAM includes: a temperature sensor for monitoring a temperature operating condition of the DRAM; and a binary counter coupled to the temperature sensor, for receiving external commands to perform a refresh operation, and incrementing a count upon each received external command, wherein the refresh operation will be selectively skipped according to a value of the binary counter. The binary counter is activated to a first mode when the temperature sensor determines the temperature operating condition of the DRAM goes below a first threshold and activated to a second mode when the temperature sensor determines the temperature operating condition of the DRAM goes below a second threshold lower than the first threshold.

Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method of managing memory includes determining a temperature associated with the memory and determining a level of write queue utilization associated with the memory. A write operation may be performed based on the level of write queue utilization and the temperature.

Abstract: A semiconductor device includes a first cell array region disposed adjacent to a second cell array region; a dummy cell region disposed between the first cell array region and the second cell array region, and configured to distinguish the first cell array region from the second cell array region by dummy bit lines; first group segment input/output lines disposed to correspond to the first cell array region when viewed in terms of the dummy bit lines; and second group segment input/output lines disposed to correspond to the second cell array region when viewed in terms of the dummy bit lines.

Abstract: A nonvolatile semiconductor memory device includes first and second word line groups, each including a plurality of stacked word lines above a substrate, a first memory string including a first memory column through the first word line group, a second memory column through the second word line group, and a first memory connection portion electrically coupling the first and second memory columns, and a second memory string including a third memory column through the first word line group, a fourth memory column through the second word line group, and a second memory connection portion electrically coupling the third and fourth memory columns. The first memory connection portion is formed in a first layer of the substrate and the second memory connection portion is formed in a second layer of the substrate that is lower than the first layer.

Abstract: The present disclosure relates to a resistance random access memory (RRAM) device architecture where a Ti metal capping layer is deposited before the deposition of the HK HfO resistance switching layer. Here, the capping layer is below the HK HfO layer, and hence no damage will occur during the top RRAM electrode etching. The outer sidewalls of the capping layer are substantially aligned with the sidewalls of the HfO layer and hence any damage that may occur during future etching steps will happen at the outer side walls of the capping layer that are positioned away from the oxygen vacancy filament (conductive filament) in the HK HfO layer. Thus the architecture in the present disclosure, improves data retention.

Abstract: A memory cell includes a first bidirectional resistive memory element (BRME), and a second BRME, a first storage node, and a second storage node. A resistive memory write to the cell includes placing the first BRME and the second BRME in complementary resistive states indicative of the value being written. During a subsequent restoration operation, the value as written in the first BRME and second BRME is written to the first storage node and the second storage node while a wordline connected to the memory cell is deasserted.

Abstract: A current generation circuit includes a mirroring circuit suitable for being charged by using a bias voltage, wherein a voltage level of the charged voltage varies corresponding to changes in a voltage level of a power voltage, a comparison circuit suitable for comparing the charged voltage with a feedback voltage, and a current driving circuit suitable for generating a current based on a voltage output from the comparison circuit.

Abstract: For non-volatile random access memory (NVRAM) power management using self-refresh commands, a low-power module intercepts a memory self-refresh command and powers down an NVRAM in response to the memory self-refresh command. A resumption module intercepts a self-refresh exit command and powers up the NVRAM in response to the self-refresh exit command.

Abstract: A bitline circuit for embedded Multi-Time-Read-Only-Memory including a plurality of NMOS memory cells coupled to a plurality of wordlines in each row, bitlines in each column, and a source-line. More specifically, the bitline circuit controls a charge trap behavior of the target NMOS memory array by mode-dependent bitline pull-down circuit, thereby discharging the bitline strongly to GND to trap the charge effectively in a Programming mode, and discharge the bitline weakly to GND to develop a bitline voltage to detect the charge trap state. The mode dependent circuit is realized by using at least two NMOS to switch the device strength, using a pulsed gate control in a Read mode, or using analog voltage to limit the bitline current. The proposed method further includes a protection device, allowing all bitline control circuit using thin oxide devices.

Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method of managing memory includes determining a temperature associated with the memory and determining a level of write queue utilization associated with the memory. A write operation may be performed based on the level of write queue utilization and the temperature.

Abstract: A nonvolatile memory device is provided. The nonvolatile memory device includes a memory cell array, an anti-fuse cell array, a sense amplifier, a page buffer, and a control logic. The memory cell array includes memory cells connected to word lines and bit lines. The anti-fuse cell array stores setting information for controlling the memory cell array. The anti-fuse cell array includes anti-fuse cells connected to the bit lines. The sense amplifier is connected to the bit lines to sense the memory cells or the anti-fuse cells. The page buffer stores data that is read out from the memory cells or the anti-fuse cells. The control logic controls the sense amplifiers and the page buffer to read out data from the memory cell array or the anti-fuse cell array.

Abstract: A data transmitting method for a memory storage apparatus is provided. The method includes: initially setting a first threshold and a first accumulated value; and updating the first threshold by using the first threshold plus the first accumulated value at intervals of a first predetermined time. The method also includes when a detected temperature of the memory storage apparatus is greater than or equal to a temperature threshold, determining whether a size of received writing data is greater than or equal to the first threshold; and if no, writing the writing data into a rewritable non-volatile memory module and then updating the first threshold by using the first threshold minus the size of the writing data; and if yes, not writing the writing data into the rewritable non-volatile memory module. Accordingly, the method can effectively prevent overheat of system during operations of the memory storage apparatus.

Abstract: A method for operating a small-area EEPROM array is disclosed. The small-area EEPROM array comprises bit lines, word lines, common source lines, and sub-memory arrays. The bit lines are divided into bit line groups. The word lines include a first word line. The common source lines include a first common source line. Each sub-memory array includes a first, second, third and fourth memory cells, which are connected with two bit line groups, a word line and a common source line. The first and second memory cells are symmetric. The third and fourth memory cells are symmetric. The group of the first and second memory cells and the group of the third and fourth memory cells are respectively positioned at two sides of the first common source line. The method operates all operation memory cells and uses special biases to program or erase memory cells massively in a single operation.

Abstract: A cell array portion of a single-layer gate EEPROM device includes a plurality of unit cells formed over a substrate to share a first well region in the substrate. Each of the plurality of unit cells includes a floating gate having a first part disposed over the first well region and a second part extending from the first part to have a stripe shape, a selection gate spaced apart from the floating gate and disposed to be parallel with the second part of the floating gate, and an active region disposed in the substrate to intersect the floating gate and the selection gate.