Abstract: Apparatus for making legacy network elements transparent to IEEE 1588 Precision Time Protocol operation. Network elements are wrapped by device(s) capable of providing either transparent clock or boundary clock operation. In one embodiment, smart interface converters are used to provide transparent clock or boundary clock operation. The smart interface converters work cooperatively.

Abstract: A signal buffering and retiming (SBR) circuit for a plurality of memory devices. A PLL-based clock generator generates a set of phase-shifted clock signals from a received host clock signal. Each of a plurality of phase selectors independently selects a subset of contiguous clock signals from the set of phase-shifted clock signals. Each subset of contiguous clock signals is applied to a different set of one or more verniers, each vernier independently selecting one of the contiguous clock signals as its retiming clock signal for use in generating either (1) an output clock signal or a retimed bit of address or control data for one or more of the memory devices or (2) a feedback clock signal for the PLL-based clock generator. The SBR circuit can be designed to satisfy relatively stringent signal timing requirements related to skew and delay.

Abstract: A clock data recovery circuit includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive data and a clock signal and to detect transitions in the data and provide a first signal based on the clock signal and the transitions in the data. The second circuit is configured to receive the first signal and provide a first shift signal based on the first signal. The third circuit is configured to receive the first shift signal, wherein the first circuit, the second circuit, and the third circuit are configured to form a first circuit loop and the third circuit is configured to disable the first circuit loop and shift the clock signal based on the first shift signal.

Abstract: A network storage appliance having a main computing unit is provided with an embedded microcomputer for monitoring startup and operation of the main computing unit. The microcomputer has the ability to restart, power down or power up the main computing unit if any corresponding predetermined conditions exist. Local nonvolatile storage holds the firmware for the main computing unit and configuration for the appliance. After loading the firmware and configuration to the main computing unit, the nonvolatile storage is electronically disconnected from the main computing unit. Where two such appliances are coupled for redundancy between the same network storage and the network, the embedded microcomputers are separately coupled for communication to allow for negotiating a restart of one of the main computing units under the direction of the other, or if any predetermined conditions occur.

Abstract: An SCP (System Control Processor) 7 is provided in addition to a CPU 1 responsible for control of circuits in a computer. Upon receiving a Main ON signal (low level) indicative of the CPU 1 being inactive, the SCP 7 responds to a switch operation on a control panel 6 to supply a CD-ROM drive 2 with a command corresponding to the switch operation on said control panel 6 independently of the CPU 1 as well as to feed a high-level CD-POWER-ON signal to a power supply circuit 8 through an OR circuit 9. The power supply circuit 8 selectively supplies the CD-ROM drive 2 and an Audio amplifier 10 with driving power upon receiving the high-level signal.

Abstract: An aggregated server blade system includes a plurality of individual server blades and a management module which can be designated as a bootable device. A boot list maintained and executed in each server blade includes a management module entry in its list of bootable devices. In response to the management module entry being selected or otherwise made active as the bootable device for a particular blade, an alternative bootable-devices list maintained on the management module is referenced and the boot process proceeds according to the alternative list.

Abstract: Methods and apparatus are disclosed to self-initialize a processor. An example method disclosed herein detects a processor reset, receives initialization instructions from a core zone, establishes a core zone boundary, executes received initialization instructions, and publishes a data structure, the data structure comprising state information. Other embodiments are described and claimed.

Abstract: A network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed. The network of microcontrollers provides a management system by which computer users can accurately gauge the health of their computer. The network of microcontrollers provides users the ability to detect system fan speeds, internal temperatures and voltage levels. The invention is designed to not only be resilient to faults, but also allows for the system maintenance, modification, and growth—without downtime. Additionally, the present invention allows users to replace failed components, and add new functionality, such as new network interfaces, disk interface cards and storage, without impacting existing users. One of the primary roles of the present invention is to manage the environment without outside involvement. This self-management allows the system to continue to operate even though components have failed.

Abstract: In accordance with one embodiment of the invention, a storage system is configured as at least one logical unit including at least one disk device; a controller for executing a read processing or a write processing of data having been stored or to be stored in the logical unit which is a destination of a read request or a write request, in response to the read request or write request transmitted from the computer, wherein the controller receives an instruction from the computer to turn on or off a disk device corresponding to the logical unit; and wherein, based on the instruction, the storage system turns on or off the disk device corresponding to the logical unit independently of disk devices corresponding to the other logical units.

Abstract: Methods, circuits, and apparatus for changing a frequency of a clock signal provided to a graphics memory while reducing any resulting visual glitch or disturbance on a monitor. A specific embodiment provides multiple clock sources that may be multiplexed or selected to provide a memory clock signal to the graphics memory. The multiplexer switches from providing a first clock source signal as the memory clock signal to providing a second clock source signal as the memory clock signal. The first clock source changes its frequency of operation. After the first clock source settles or stabilizes, the multiplexer switches back to providing the first clock source signal as the memory clock signal.

Abstract: A file display system is provided. The file display system includes a MCU (10), a display control unit (20) and a display unit (30). The MCU receives power-on commands and power-off commands from a control unit (50). According to the preferred embodiment, upon receiving a power-off command, the MCU reads a next page data content of a currently displayed page from a storage apparatus (40) and stores the next page data content in the display control unit; and upon receiving a following power-on command, the MCU enables the display control unit, and the display control unit controls the next page data content stored therein to be displayed on the display unit, the next page data content therefore becomes a currently displayed page. A related method is also provided.

Abstract: A system and methods for connecting a graphic user interface to a powered network is disclosed. The network-powered graphic user interface system converts encoded computer user interface signals transmitted over a powered network cable to multiple signal sets, each set associated with a peripheral device interface. Methods for managing the admission of the peripheral devices are also described. Connection criteria include the power budget for the connection, device characteristics, device power requirements and the characteristics of other devices sharing the powered network connection.

Abstract: A processor comprises a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data amount detector detecting amounts of the data stored in the storage per each execution unit; a clock frequency determining part determining a new clock frequency of the clock signals by using the amounts of the data, said clock signals being supplied newly to the operational processing part.

Abstract: A processor comprises a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data amount detector detecting amounts of the data stored in the storage per each execution unit; a clock frequency determining part determining a new clock frequency of the clock signals by using the amounts of the data, said clock signals being supplied newly to the operational processing part.

Abstract: In response to an instruction to shut down a first operating system, the first operating system is shut down, and then a second operating system whose function is limited as compared with the first operating system is activated, and by the activation, the data stored in the memory is saved and a power-saving state is immediately entered, thereby automatically allowing the second operating system to be transferred to a state in which quick activation can be performed.

Abstract: A PLD is interposed on the communication route between a microprocessor (hereinbelow called MP) and boot memories. The boot memories store MP start-up data needed to start up the MP and start-up protection code constituting protection code for the MP start-up data. The PLD reads the MP start-up data and the start-up protection code thereof from the boot memories, performs, in hardware fashion, a check of the validity of the MP start-up data using this start-up protection code and, if a negative check result is obtained, resets the MP and if a positive check result is obtained, inputs the start-up data that is thus read to the MP.

Abstract: A reset device for a computer system is provided. The reset device includes a hardware-reset signal generating circuit for outputting a hardware-reset signal to reset the computer system, a first switch, and a second switch having a first contact, a second contact, and a third contact. The third contact can be selectively electrically connected to the first contact to enable the hardware-reset signal generating circuit to output the hardware-reset signal when the first switch is turned on, or the second contact to output a software-reset signal to a central processing unit of the computer system when the first switch is turned on.

Abstract: A host apparatus that adjusts consumption of a device in accordance with the power supply capability of the host apparatus. The host apparatus includes a plurality of communication ports and devices connected to each communication port. A host controller of the host apparatus communicates with the devices to acquire equipment information including the consumption current of each device. A current supply circuit supplies current to the devices connected to the communication ports. An MPU changes the current supplied from the current supply circuit to the plurality of devices when a total value of the consumption current of a device newly connected to the plurality of communication ports and the consumption current of each device for which connection with the plurality of ports has already been recognized exceeds the current that the current supply circuit is capable of supplying.

Abstract: A system for booting a computing device with a windowing operating system obtained from an external memory media via an external interface includes an initialization module stored in a read-only memory in the computing device, the module being executed in a processor in the computing device and establishing a data connection to the external memory media through the external interface, and an external device in which the external memory media is disposed, the media storing a windowing operating system image at an external location, and sending the image from the media to the computing device via the external interface in response to a request from the computing device based on memory geometry information of the media, the image being received by the computing device, loaded into a runtime memory in the computing device and then executed by the processor to boot the windowing operating system in the computing device.

Abstract: A radio frequency generating system comprises a synchronization board that receives an external clock signal from a clock source and generates multiple copies of the external clock signal. Each of a plurality of signal generation board receives a copy of the external clock signal from the synchronization board. Each signal generation board comprises a plurality of direct digital synthesizers that are synchronized using the external clock signal.