Abstract: A memory module comprises a memory device including a memory array to store data. An interface receives an instruction to exit a power down mode. A register stores a value representative of a period of time to elapse between exiting from the power down mode and a time at which the memory device is capable of receiving a command to access the data. A storage device stores a plurality of parameter information that pertains to the memory device. The value is based on at least a first parameter information of the plurality of parameter information.

Abstract: Adaptive thresholding technique for power supplies during margining events. A power supply may include a fault detection mechanism for monitoring an output voltage of the power supply to determine whether the output voltage is greater than a first over-voltage threshold or less than a first under-voltage threshold. If a margining event changes the power supply output voltage, the fault detection mechanism may dynamically change a first over-voltage threshold and a first under-voltage threshold based on the margining event to a second over-voltage threshold and a second under-voltage threshold. Then, during the margining event, the fault detection mechanism may monitor the output voltage of the power supply to determine whether the output voltage is greater than a second over-voltage threshold or less than a second under-voltage threshold. The fault detection mechanism may dynamically change a fault threshold in proportion to the change in the power supply output voltage.

Abstract: A user agent in a Web access device transmits an HTTP request for Web content to an origin server. The request contains a set of capabilities of the Web access device. A content authoring mechanism and adaptation determination service on the origin server process the request to determine what transformation is required to make the requested content fit the capabilities of the Web access device. The adaptation determination service invokes a niche transformation service that performs, in response to the content and the capabilities, the necessary transformation. The transformed Web content is transmitted to the user agent.

Abstract: A power saving method and system thereof is disclosed. When the central processing unit is under a non-snooping sleep state and a peripheral device sends a bus master request, a chip will drive the central processing unit waking from the non-snooping sleep state and entering a system management mode for executing an interrupt service routine that makes the central processing unit in halt status. The central processing unit is then driven to enter a snooping sleep state for snooping the bus master request. After the execution of the bus master request, the chip will drive the central processing unit to leave the snooping sleep state and return to the non-snooping sleep state for power consumption conservation.

Abstract: A computer motherboard has a central processor socket, memory sockets, and a plurality of connectors for connecting peripheral devices to the motherboard. Two or more storage ports enable connection of storage devices (e.g., HDDs) to the motherboard. A system BIOS that is resident on the motherboard contains computer-executable program code for enabling backup and restore functionality on the storage devices connected to the storage ports.

Abstract: Methods are provided for retargeting captured images to new hardware. An image taken from a computer having hardware drivers and other system information in one hardware configuration can be modified to adapt it for use on a computer having different hardware requiring different drivers, even when the second hardware configuration was not known at the time of imaging. Systems and configured storage media for retargeting captured images to new hardware are also provided.

Abstract: A switching circuit located in a computer system is disclosed in the present invention. The switching circuit comprises a first phase-locked loop generating a first host clock signal, a second phase-locked loop generating a second host clock signal and an output switch unit coupled to the first PLL and the second PLL. When the computer system operates in a first mode, the output switch unit chooses the first host clock signal to be a fundamental clock signal of the front side bus. In the other hand, when the computer system operates in a second mode, the output switch unit chooses the second host clock signal to be a fundamental clock signal of the front side bus.

Abstract: Adaptive control of operating and body bias voltages. In accordance with a first embodiment of the present invention, a desirable operating frequency for the microprocessor is determined. Information stored within and specific to the microprocessor is accessed. The information can comprise coefficients of a quadratic approximation of a frequency-voltage characteristic of the microprocessor for a set of body biasing conditions. An efficient voltage for operating the microprocessor at the desirable operating frequency is computed. The microprocessor is operated at the efficient voltage and the set of body biasing conditions.

Abstract: An exemplary CPU frequency regulating circuit includes a detecting circuit, a comparing circuit, and an adjusting circuit. The detecting circuit is coupled to a power circuit of a CPU for receiving and amplifying a load voltage. The comparing circuit is coupled to the detecting circuit for comparing the amplified load voltage with a default voltage. The adjusting circuit is coupled between the comparing circuit and the CPU for selecting a CPU frequency according to a result of the comparison. The CPU frequency regulating circuit detects the load voltage of the power circuit of the CPU for selecting an appropriate frequency to the CPU according to a working condition.

Abstract: The present disclosure describes exemplary embodiments of BIOS-based systems and methods of processor power management. Such systems include a computer system, comprising: a processor operable at a plurality of power levels (the processor comprises a register capable of storing a processor load value); a memory coupled to the processor; and BIOS software stored in the memory that executes on the processor, (the BIOS software comprises a power management module). The power management module sets the processor to a new power level of the plurality of power levels if a function of the load value indicates the new power level.

Abstract: A portable information handling system having internal battery power and external adapter power manages power drawn from the external power adapter to avoid exceeding the power rating of the external power adapter. As power drawn from the external adapter approaches a predetermined limit of the power adapter power rating, a power manager of the information handling system alters the operation of the information handling system to reduce power drawn from the adapter, such as by reducing current drawn to charge the battery, enforcing battery optimized mode steps or throttling central processing unit operation. Incremental decreases in power consumption maintain power draw below the external adapter power rating while incremental increases in power consumption have a delay that returns the information handling system to normal operations without excessive oscillation between operating modes.

Abstract: A memory system comprises an encryption engine implemented in the hardware of a controller. In starting up the memory system, a boot strapping mechanism is implemented wherein a first portion of firmware when executed pulls in another portion of firmware to be executed. The hardware of the encryption engine is used to verify the integrity of at least the first portion of the firmware. Therefore, only the firmware that is intended to run the system will be executed.

Abstract: A method, computer program product, and a data processing system for maintaining operation of the data processing system in the event of a degraded system cooling condition is provided. A first temperature of a processor is identified as equaling or exceeding a processor throttling threshold. The operational frequency of the processor is reduced by a first frequency increment. The operational voltage of the processor is then reduced by a first voltage increment. Updated values of the processor temperature are periodically obtained and continued reductions in the frequency and operational voltage are made until the temperature indicates that the processor is operating in a stable throttle range. The frequency and operational voltage of the processor may be returned to normal levels when an updated temperature of the processor is less or equal to a throttle off threshold.

Abstract: A method for recording the use time of a computer system is disclosed. The method includes storing the last power-on time of the computer system before shipping (the base use time) and a time variable in the basic input/output system (BIOS). Moreover, the time variable is increased every time a periodic interrupt takes place. The total use time of the computer system is then calculated according to the time variable and the periods of the periodic interrupt. Thus, the base use time and the total use time can be shown on the BIOS setup menu. Therefore, the method is able to achieve the purpose of recording the time and date when the computer system is turned on for the last time just before shipping and the total operating time of the computer system after shipping.

Abstract: A first storage system comprises an information processing device and a first volume, and is connected to an information processing device. A second storage system comprises a second volume and is connected to the first storage system. The second storage system performs power supply control relating to the second volume in cooperation with a remote copy, such that the remote copy and the power supply control are performed efficiently. Thus, a remote copy function performs power supply control of an HDD comprising a secondary volume of a remote copy pair, to match data copy status (such as stopping data copy to the secondary volume, or differential copying). Thus, longevity of the HOD and lower use of active power of a storage system can be realized.

Abstract: In one embodiment, a method is provided. The method of this embodiment provides monitoring one or more sensor outputs of a sensor, the sensor to measure a power consumption property of the chip, and each sensor output to indicate a measurement of the power consumption property; and recording a time that each of the one or more sensor outputs indicates an existence of the power consumption property at the measurement corresponding to each of the one or more sensor outputs.

Abstract: The present invention relates to an information processing apparatus capable of executing plug and play processing for starting up one installation processing operation upon acquiring one device identification information item. The information processing apparatus includes an acquisition unit for acquiring at least one device identification information item including a plurality of configuration information items corresponding to each of a plurality of logical interfaces in response to connection of a peripheral device. The information processing apparatus further includes an installation control unit for controlling execution of installation of a plurality of device drivers corresponding to the plurality of logical interfaces, respectively, by the use of the plurality of configuration information items included in the at least one device identification information item when the acquisition unit acquires the at least one device identification information item from the peripheral device.

Abstract: Two or more circuits (e.g. processing cores of a graphics processor) operate synchronously at a fast clock frequency. A core interface to each of the processing cores is designed to communicate in synchronous fashion with one or more other core interfaces at a slow clock frequency. The fast clock is distributed to each processing core in a manner that provides minimized skew and jitter, e.g. with a balanced tree network. The slow clock is locally derived from the fast clock in each core interface. One of the core interfaces is selected to provide a synchronism signal, and the synchronism signal is distributed among the multiple core interfaces to synchronize the locally derived slow clocks.

Abstract: A power supply module removably disposed within an automated data storage and retrieval system. An automated data storage and retrieval system which includes one or more power supply modules removably disposed therein. An accessor movably disposed with an automated data storage and retrieval system comprising a gripper mechanism which can be releaseably attached to a power supply module. A method to supply power to an automated data storage and retrieval system. A method to monitor the operation of a power supply module removably disposed within an automated data storage and retrieval system.

Abstract: A data transfer apparatus includes at least one master and a plurality of slaves connected by a ring-connection bus, and a controller having a master port and slave ports connected to the corresponding master and slaves, respectively. In such a ring-like structure, a large amount of data can be transferred efficiently, and even if data continuously flows on the bus, data transfer is performed in a master/slave structure, thereby reducing the overall data transfer time.