Abstract: In some embodiments, the invention involves a system and method relating to managing power utilization in partitioned systems. In at least one embodiment, the present invention is intended to control the sleeping/wakefulness of devices, as necessary, to minimize power utilization of devices whose accesses are routed away. Inter-partition communication is used to utilize devices in a sequestered partition while devices in the OS partition are put into a sleep state to save power. Other embodiments are described and claimed.

Abstract: The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.

Abstract: In a recording device having one or more semiconductor memories mounted thereon, the number of semiconductor memories operating in parallel is restricted according to an available supply current of an accessing apparatus to which the recording device is attached.

Abstract: A method and apparatus for retrieving dynamic content over a communications network prior to booting an operating system is presented. The content may include a screen image for display on a console. The time period for displaying the content may be controlled by another computer coupled to the communications network. The content may be an advertisement that is displayed on a computer system in an Internet café for a controllable period of time prior to booting an operating system.

Abstract: A method and apparatus for current detection for microelectronic devices using source-switched sensors. An embodiment of a current detector for a microelectronic device includes a first voltage sensor and a second voltage sensor. The first voltage sensor is to measure a first voltage of the microelectronic device during a first time period and a second voltage of the microelectronic device during a second time period. The second voltage sensor is to measure the second voltage during the first time period and the first voltage during the second time period. A voltage value is equal to the sum of the first voltage measured by the first sensor plus the first voltage measured by the second sensor, minus the sum of the second voltage measured by the first sensor plus the second voltage measured by the second sensor. Other embodiments are also described and claimed.

Abstract: Suppression malfunction of an authentication circuit for authenticating a battery pack. Signal line for applying an intermediate potential between the power supply and ground and for reading the potential of a thermistor for detecting the temperature is used as a transmission path for exchanging data between a battery pack and main device. A master-authentication circuit and slave-authentication circuit comprise level-correction circuits, which are connected to the signal line by way of a voltage-comparator circuit. The level-correction circuits are constructed such that they correct the signal applied to the signal line so that it is greater than or less than the unstable-region voltage, and outputs it to the input end of the authentication circuits, so that unstable-region voltage is not applied to the input end.

Abstract: A microelectronic device according to the present invention is made up of two or more functional units, which are all disposed on a single chip, or die. The present invention works on the strategy that all of the functional units on the die are not, and do not need to be operational at a given time in the execution of a computer program that is controlling the microelectronic device. The present invention on a very rapid basis (typically a half clock cycle), therefore, turns on and off the functional units of the microelectronic device in accordance with the requirements of the program being executed. This power down can be achieved by one of three techniques; turning off clock inputs to the functional units interrupting the supply of power to the functional units, or deactivating input signals to the functional units.

Abstract: In a network device, a power potential rectifier is adapted to conductively couple a network connector to an integrated circuit that rectifies and passes a power signal and data signal received from the network connector. The power potential rectifier regulates a received power and/or data signal to ensure proper signal polarity is applied to the integrated circuit.

Abstract: Reducing power while in standby mode may comprise monitoring for an occurrence of at least one event requiring a transition out of a standby mode while utilizing a lower frequency, less accurate, and low power standby clock signal while operating in the standby mode. After receiving the occurrence of the event, an identity of the received event may be determined. In response to receiving the event, based on the determined identity of the event, a first and/or a second clock signal may be enabled, which has higher frequency and better accuracy and consumes more power than the standby clock signal. If the first and/or second clock signal is enabled, they may be disabled in order to re-enter the standby mode, which utilizes the standby clock signal while in standby mode.

Abstract: Various embodiments are disclosed relating to power-efficient techniques for invoking a co-processor. In an example embodiment, a computer system may include a first processor (e.g., a host processor) and a second processor (e.g., a co-processor). The first processor may instruct the second processor to perform an operation repeatedly on a data stream. The first processor may be placed in a low power state. The second processor may perform the operation repeatedly on the data stream while the first processor remains in the low-power state.

Abstract: A method for reconfiguring an RTC time of a computer is disclosed. The method includes the steps of: storing an initial real time clock (RTC) time when the computer is powered on; calculating a first elapsed time tracked from the initial RTC time and a second elapsed time tracked from the initial RTC time; reading an RTC time of the computer after a time span of the first elapsed time; detecting whether the RTC time equals the sum of the initial RTC time and the first elapsed time; and adjusting a current RTC time of the computer after a time span of the second elapsed time to the sum of the initial RTC time and the second elapsed time, if the RTC time doesn't equal to the sum of the initial RTC time and the first elapsed time. A related system is also disclosed.

Abstract: The present invention provides processing systems, apparatuses, and methods that access a scratch pad on-demand to reduce power consumption. In an embodiment, an instruction fetch unit initiates an instruction fetch. When a scratch pad is enabled, an instruction is retrieved from the scratch pad in parallel with a translation of a virtual address to a physical address. If the physical address is associated with the scratch pad, the retrieved instruction is provided to an execution unit. Otherwise, the scratch pad is disabled to reduce power consumption and the instruction fetch is re-initiated. When the scratch pad is disabled, an instruction is retrieved from another instruction source, such as an instruction cache, in parallel with the translation of the virtual address to the physical address. If the physical address is associated with the scratch pad, the scratch pad is enabled and the instruction fetch is re-initiated.

Abstract: In a computer system having a power supply, processor, and additional subcomponents that are powered by the power supply, a method for estimating the total power requirements of the system under a variety of operating modes and configurations. In an exemplary embodiment, information concerning power requirements for each subcomponent under its operating modes is stored within non-volatile memory within the subcomponents. This information is accessed by the processor during the boot sequence, and if the information is not available, substitute information is provided. The compiled information is tabulated to compute the estimated total power requirement of the current hardware configuration. A display of this information, along with configuration selection rules, enables the user to select alternative operating modes and configurations and to show the resulting estimated power requirements.

Abstract: A system and method for providing interleaving point-of-load (POL) regulators such that each regulator's switching cycle is phase displaced with respect to those of other POL regulators in the array is disclosed. As a result, the aggregate input and/or output reflected ripple and noise of the input, output, or both is reduced. Each regulator in the array is associated with an unique address. A serial data-line writes the phase spacing programmed to each addressable POL regulator in the array. The present invention permits phase displacement of POL regulators without limitation to the input and output voltages of each of the regulators in the array. The array of POL regulators may also operate in a phase displaced mode with only a single control line. The need for separate controllers and multiple control lines is thereby eliminated.

Abstract: A memory system and corresponding method for executing boot code stored therein are provided, the memory system including a mode decoder, a first memory in signal communication with the mode decoder, a second memory in signal communication with the mode decoder, and a mode generator in signal communication with the mode decoder for generating a signal indicative of selecting one of the first and second memories as the boot memory; and the method for executing boot code including initially booting the system from a first memory, programming a second memory for subsequent booting, programming a mode generator to subsequently boot the system from the second memory, and subsequently booting the system from the second memory.

Abstract: In the case where a disk storing firmware for rewriting is used to upgrade firmware stored in a flash memory, byte codes #15, #16 of the disk corresponding to a reserve code (byte codes #15, #16) of the flash memory are ignored. Specifically, byte codes #1 to #14 of the flash memory are compared with byte codes #1 to #14 of the disk. If all codes match each other, it is determined that the firmware of the disk is firmware of a compatible model and a rewrite operation is started. Therefore, under the condition that the disk device is of a compatible model, the firmware of the device can be upgraded and thus the firmware is improved in compatibility.

Abstract: Methods and apparatus are disclosed for balancing power across all conductors of an Ethernet connection. Balancing circuitry is disclosed to allow an Ethernet midspan device to receive power from an Ethernet Power Sourcing Equipment (PSE) on the signal pairs of an Ethernet connection. The balancing circuitry is configured to sense the level of the received power, and generate a second power source substantially equal to the received power level. The received power is provided to an Ethernet Powered Device (PD) over the signal pairs of an Ethernet connection, and the generated power to the PD over the unused pairs of the Ethernet connection.

Abstract: A data processing system allows processes to be checkpointed and restarted. The system saves the old process and thread identifications in a process table. When an application makes a system cell passing the old process and/or thread identifications as parameters, the system performs a mapping algorithm to supply the system call with the new process and/or thread identifications. When a system call returns a new identification, the system performs a remapping algorithm to return the old identifications to the calling application program. When a group of process is restarted for which the process group leader was not checkpointed, the system creates a ghost process group leader.

Abstract: An integrated circuit includes a phase-locked-loop with fast clock synchronization recovery. A phase frequency detector is configured to receive a system clock signal and a feedback clock signal and to generate a comparison signal. A clock generator is configured to general a first clock signal based on the comparison signal, and an internal clock signal. A controller coupled to the clock generator and configured to deliver a mesh clock signal to a global clock mesh. A synchronizer coupled to the control logic and configured to generate a feedback clock signal to the phase frequency detector. The mesh clock signal is provided from the global clock mesh to the synchronizer. Advantages of the invention include the ability to operate the integrated circuit in a sleep state with a slow clock rate and then quickly recover to an operational clock rate.

Abstract: Memory storage apparatus include a non-volatile memory for storing data and a power management unit configured to sense a level of an external power supply and to predict a loss of the external power supply. A power-polling time control circuit is configured to control a time when a voltage level sourced from the external power supply is reduced below a predetermined level after loss of the external power supply. A control logic controls read and/or write operations of the non-volatile memory responsive to a prediction of loss of the external power supply from the power management unit.