Abstract: At least two ramp-edge-structure Josephson junctions having different critical current densities to one another are provided on a substrate.

Abstract: A laminated structure with less breakage of an insulative layer due to stress and easy interconnection. The laminated structure includes at least a first electrode layer, a dielectric layer and a second electrode layer stacked in this order. The first electrode layer includes a first electrode material disposed such that an end surface thereof is exposed in a first side region of the laminated structure and a second electrode material having an insulating film formed on an end surface in a second side region of the laminated structure. The second electrode layer includes the first electrode material disposed such that an end surface is exposed in the second side region of the laminated structure and the second electrode material having an insulating film formed on an end surface in the first side region of the laminated structure.

Abstract: An ESD protection circuit is adapted for an integrated circuit with a first power source and a second power source. The ESD protection circuit comprises a first silicon controlled rectifier (SCR), a second silicon controlled rectifier, and a parasitic diode. The gate of the first silicon controlled rectifier is coupled to a first power source, and the gate of the second silicon controlled rectifier is also coupled to the first power source line.

Abstract: There is provided a transistor and a method of manufacturing this transistor that allow a high degree of freedom when designing a wiring structure and also allow an improvement in product quality to be achieved. The transistor includes a source area, a drain area, and a channel area, each of which are formed by semiconductor films, and also a gate insulating film and a gate electrode. The semiconductor film containing the source area and the semiconductor film containing the drain area are formed separately sandwiching both sides of an insulating member. The semiconductor film containing the channel area is formed on top of the insulating member.

Abstract: It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, disclosed is a method in which, e.g., a high density plasma silicon oxide film is deposited on wirings (e.g., a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell) by means of a high density plasma CVD technique, at a first temperature, and the structure is subjected to RTA (heat treatment) at a second temperature higher than the first temperature (e.g., 750° C.). Via holes are then formed in the high density plasma silicon oxide film, and first and second conductive films are then formed, the first conductive film being formed in the via holes and at a third temperature lower than the first temperature. The first and second conductive layers are then polished to remain selectively within the via holes.

Abstract: Some embodiments provide a semiconductor substrate having a cell array region and a peripheral circuit region. A plurality of word line patterns are placed in the cell array region, each of which include a word line and a word line capping layer pattern stacked thereon. At least one gate pattern including a gate electrode and a gate capping layer pattern is formed in the peripheral circuit region, the gate capping layer pattern and the word line capping layer pattern having different etching selectivity ratios. A pad interlayer insulating layer and a bit line interlayer insulating layer having approximately the same etching selectivity ratio as the gate capping layer pattern are sequentially formed over a surface of the semiconductor substrate having the gate spacers.

Abstract: A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.

Abstract: The present invention provides collarless trench semiconductor memory devices having minimized vertical parasitic FET leakage and methods of forming the same.

Abstract: The present invention provides a thin channel MOSFET having low external resistance. In broad terms, a silicon-on-insulator structure comprising a SOI layer located atop a buried insulating layer, said SOI layer having a channel region which is thinned by the presence of an underlying localized oxide region that is located on top of and in contact with said buried insulating layer; and a gate region located atop said SOI layer, wherein said localized oxide region is self-aligned with the gate region. A method for forming the inventive MOSFET is also provided comprising forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.

Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

Abstract: A dense array of semiconductor devices having an array of micro-reflectors, the micro-reflectors having characteristics that enhance dense packing of the array in balance with collection and collimation of the array's radiant output.

Abstract: A High Intensity LED is disclosed to include a metal base, which has a through hole extending between the top and bottom surfaces thereof and a first electrode formed integral with and downwardly extending from the bottom surface, a second electrode inserted through the through hole and isolated from the metal base with an electrically insulative sleeve, an LED chip mounted on the top surface of the metal base and electrically contacting with the top surface of the metal base and the LED chip electrically connected to the top end of the second electrode with at least one gold wire, and an electrically insulative packaging shell surrounding the metal base and the LED chip excluding the first electrode and the bottom end of the second electrode. Red, green and/or blue color LED chips may be in contact with the top surface of the metal base to produce High Intensity light.

Abstract: The semiconductor device comprises an interconnection buried in an interconnection groove formed in a lower insulating film, and an upper insulating film having a contact hole formed down to an end part of the interconnection. The interconnection groove is formed by using a design pattern having a main interconnection portion 100 and an extended portion 104 provided at an end part of a main interconnection portion 100 for forming the interconnection and extended perpendicularly to an extending direction of the main interconnection portion 100.

Abstract: Disclosed are a semiconductor device and method of manufacturing the same comprising a substrate, a mesa region adjacent to the substrate, an electroplated metal layer, for reducing the thermal resistance of the device, surrounding the mesa region, an insulator layer separating a side portion of the mesa region from the electroplated metal layer, a heat sink, a bonding layer adjacent to the heat sink, and a second metal layer in between the substrate and the heat sink, wherein the substrate is adjacent to the bonding layer, and wherein the electroplated metal layer dimensioned and configured to have a thickness of at least half a thickness of the mesa region; and to laterally spread heat away from the mesa region. The mesa region comprises a first cladding layer adjacent to the substrate, an active region adjacent the first cladding layer, and a second cladding layer adjacent to the active region.

Abstract: A semiconductor device includes a transfer channel for transferring charge generated by photoelectric conversion, an insulating film formed on the transfer channel, and a transfer electrode for applying a transfer voltage to the transfer channel via the insulating film. The insulating film has the first thickness and a second thickness that is thinner than the first thickness. The insulating film has the first thickness below both ends of the transfer electrode in a width direction of the transfer channel that is orthogonal to a charge transfer direction through the transfer channel, and the insulating film has the second thickness on a part including a center of the transfer channel in the width direction.

Abstract: A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is flip-chip bonded and electrically connected to the carrier or another chip. There is a flip-chip bonding gap between the chip and the carrier or other chips. A heat sink is positioned on the uppermost chip. The encapsulating material layer fills the flip-chip bonding gap as well as a gap between the uppermost chip and the heat sink. A part of the surface of the heat sink away from the upper-most chip is exposed. Furthermore, the encapsulating material layer is formed in a simultaneous molding process. For example, the chip is separated from the heat sink by a distance between 0.03˜0.2 mm, and the encapsulating material has a thermal conductivity greater than 1.2 W/m.K.

Abstract: A semiconductor device includes: a semiconductor substrate in which a semiconductor element is formed; a multilayer structured wiring layer that is provided on the semiconductor substrate, the wiring layer forming a structure connected with the semiconductor element; a spiral inductor that is formed in at least one layer of the wiring layer; and a connection terminal formed in an uppermost layer of the wiring layer for establishing connection from the wiring layer to an outside such as a printed board. A shielding wiring pattern is disposed between the spiral inductor and the connection terminal, the shielding wiring pattern functioning as an electromagnetic shield for the uppermost layer of the wiring layer. The shielding wiring pattern absorbs a change in electrical field caused by a potential change in the connection terminal, providing a shielding structure which suppresses the superposing of noise and an unnecessary signal onto the spiral inductor from the connection terminal.

Abstract: Ferroelectric memory devices and methods for fabricating such devices are provided. The ferroelectric memory device may comprise one or more interlayer dielectric layers on a semiconductor substrate, an oxygen-diffusion barrier pattern on the interlayer dielectric layer(s), and an upper insulating layer that is on the interlayer dielectric layer(s) that at least partially surrounds the oxygen-diffusion barrier pattern. These devices further include a capacitor that has a bottom electrode that is on the oxygen-diffusion barrier layer and on at least a portion of the upper insulating layer, a ferroelectric layer that is on the bottom electrode, and a top electrode that is on the ferroelectric layer. In some embodiments of the present invention, the top surface of the upper insulating layer is higher than the top surface of the oxygen-diffusion barrier pattern.

Abstract: A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a <110> crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a <100> crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a <110> crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.

Abstract: A solid state p-n heterojunction comprising an electron conductor and a hole conductor; it further comprises a sensitising semiconductor, said sensitizing semiconductor being located at an interface between said electron conductor and said hole conductor. In particular, the sensitizing semiconductor is in form of quantum-dots. A solid state sensitized photovoltaic cell comprises such a heterojunction between two electrodes.