Abstract: A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain orientation. Finally, an aluminum film is formed on the second layer of titanium nitride. Optionally, a titanium silicide layer is formed on the semiconductor structure prior to the step of forming the first layer of titanium nitride. Interconnects formed according to the invention have polycrystalline aluminum films with grain sizes of approximately less than 0.25 microns.

Abstract: A vertical-current-flow resistive element includes a monolithic region having a first portion and a second portion arranged on top of one another and formed from a single material. The first portion has a first resistivity, and the second portion has a second resistivity, lower than the first resistivity. To this aim, a monolithic region with a uniform resistivity and a height greater than at least one of the other dimensions is first formed; then the resistivity of the first portion is increased by introducing, from the top, species that form a prevalently covalent bond with the conductive material of the monolithic region, so that the concentration of said species becomes higher in the first portion than in the second portion. Preferably, the conductive material is a binary or ternary alloy, chosen from among TiAl, TiSi, TiSi2, Ta, WSi, and the increase in resistivity is obtained by nitridation.

Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The process flow may include forming an inter-layer dielectric with spray coating or lamination over a surface with high aspect ratio structures.

Abstract: A photo-sensing device package is provided. The package includes a substrate, at least one photo-sensing semiconductor die coupled to the substrate, and a patterned layer formed on a light receiving surface of the substrate. The substrate is formed of a material substantially transparent to light within a predetermined range of wavelengths, provided with front and backside surfaces on opposite sides thereof. The photo-sensing semiconductor die defines at least one photo-sensing area opposing the substrate front surface for receiving light impinging upon the substrate's backside surface and passing therethrough. The patterned layer is formed on the substrate's backside surface for blocking passage of at least a portion of the light otherwise impinging upon that backside surface, and is formed with a window opening aligned with at least a portion of the photo-sensing area for optical communication therewith through the substrate.

Abstract: To provide a light emitting device having a high reliability wherein no resin burrs occur, The semiconductor device comprises a semiconductor element, a package having a recess for housing the semiconductor element and a mold member for sealing the semiconductor element in the recess and the package comprises lead electrodes and a package support part supporting the lead electrodes so that main surfaces of the tip portions of the lead electrodes are exposed from the bottom surface of the recess.

Abstract: A semiconductor component has at least one first terminal zone of a first conductivity type in a semiconductor body. The first terminal zone is contact-connected by a first terminal electrode. A drift zone of the first conductivity type is adjoined by a second terminal zone of the second conductivity type. A channel zone of a second conductivity type is formed between the at least one first terminal zone and the drift zone. A control electrode is insulated from the semiconductor body and adjacent to the channel zone. A first channel is formed by the channel zone in a region adjacent to the control electrode, the first channel conducts only upon application of a control voltage that is not equal to zero between the control electrode and the first terminal zone. The first terminal electrode is connected to the drift zone via at least one second channel of the first conductivity type, which already conducts in the event of a control voltage equal to zero.

Abstract: A first transistor has a first main electrode region which is formed so that these are subdivided into a plurality of first isolated island region. A second transistor has its first main electrode region which are divided into a plurality of second isolated island regions in close proximity to the array of first island regions.

Abstract: An insulating film covering a Cu interconnection is formed. A contact hole which partially exposes the surface of the Cu interconnection is formed in the insulating film. A series of steps (steps (a) to (d)) including (a) a step of continuously supplying WF6 gas for a predetermined time, (b) a step of continuously exhausting the WF6 gas atmosphere for a predetermined time, (c) a step of continuously supplying SiH4 gas for a predetermined time, and (d) a step of continuously exhausting the SiH4 gas atmosphere for a predetermined time, is repeatedly executed to form W nuclei in the contact hole. Then, a W film is buried into the contact hole. This interconnection structure formation method can reliably bury the W film into the contact hole while preventing Cu elution from the Cu interconnection to the W plug.

Abstract: A semiconductor connection substrate which connects a semiconductor element to a mounting substrate such as a printed substrate comprises an insulator substrate, a plurality of electrodes having different areas provided on the insulator substrate, one or more elements selected from a capacitor element of dielectric material sandwiched between the electrodes, an inductor element and resistor element, a metal wiring connecting the elements, a metal terminal part of part of the metal wiring and an organic insulator material covering the elements and the circumference of the metal wiring portion excluding the metal terminal portion.

Abstract: A semiconductor device wiring structure is provided to reduce the wiring inductance and curtail the generation of interfering electromagnetic waves. A semiconductor chip having an anode electrode and a cathode electrode provided on two oppositely-facing main surfaces is sandwiched between a sheet-shaped anode wiring and a sheet-shaped cathode wiring. The anode and cathode electrodes of the semiconductor chip are connected to the anode and the cathode wirings, respectively, arranged such that the electric currents flowing there-through flow in opposite directions. A conductive substrate having a main surface with a larger width than the cathode wiring is disposed adjacent to the anode wiring. The edges of the cathode wiring protrude beyond the edges of both the anode wiring and the semiconductor chip in all locations and the dimension of the protrusion is at least one half of the distance from the edge of the cathode wiring to the metal substrate.

Abstract: Provided is a semiconductor device including a silicon substrate, a gate insulator disposed on the silicon substrate and containing a metal oxide, a gate electrode disposed on the gate insulator, and a sidewall insulating film disposed on a side of the gate insulator and the gate electrode and containing aluminum, silicon, oxygen and nitrogen.

Abstract: The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.

Abstract: A thin film transistor substrate includes a transparent insulating substrate, a first thin film transistor that is formed on the transparent insulating substrate, and a second thin film transistor that is formed on the transparent insulating substrate. The second thin film transistor has a characteristic that differs from that of the first thin film transistor. An active layer of the first thin film transistor has a thickness greater than or equal to 50 nm, and an average crystal grain diameter greater than or equal to 1 ?m. An active layer of the second thin film transistor has a thickness less than or equal to 60 nm, and an average crystal grain diameter less than 1 ?m. The thin film transistor substrate is formed by conducting poly-crystallization through CW laser irradiation while controlling off time leak current generation and pressure resistance degradation.

Abstract: A trench MIS device is formed in a semiconductor die that contains a P-epitaxial layer that overlies an N+ substrate and an N-epitaxial layer. In one embodiment, the device includes a drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. A termination region of the die includes a half-trench at an edge of the die and an N-type region that extends from a bottom of the half-trench to the substrate. An insulating layer and an overlying metal layer extend from the surface of the epitaxial layer into the half-trench. Preferably, the elements of the termination region are formed during the same process steps that are used to form the active elements of the device.

Abstract: A chip having a microelectromechanical system fabricated thereon is disclosed that has both perimeter off-chip electrical contacts, as well as interior off-chip electrical contacts. The interior off-chip electrical contacts are not used for directing an off-chip signal onto the chip, or for reading out an on-chip a signal to an off-chip location. Instead, these interior off-chip electrical contacts are the result of an efficient way of designing the layout of die on a wafer from which the chip may be diced.

Abstract: A bipolar transistor is provided, which is low in collector-to-emitter saturation voltage, small in size and to be manufactured by a reduced number of processes, and a semiconductor device formed with such a bipolar transistor and a MOS transistor on a same substrate. A high concentration region for reducing the collector-to-emitter saturation voltage VCE(sat) is formed in a manner surrounding a base region of an NPN transistor. This high concentration region is not necessarily formed in such a depth as reaching a buried layer, and can be reduced in the spread in a lateral direction. Because a high concentration region can be formed in a same process as upon forming source and drain regions for an NMOS transistor to be formed together with an NPN transistor on a same silicon substrate, it is possible to omit a diffusion process exclusive for forming a high concentration region and hence to manufacture a semiconductor device through a reduced number of processes.

Abstract: A self-aligned magnetic clad bit line structure (274) for a magnetic memory element (240a) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure (274) extends within a trench (258) and includes a conductive material (264), magnetic cladding sidewalls (262) and a magnetic cladding cap (252). The magnetic cladding sidewalls (262) at least partially surround the conductive material (264) and the magnetic cladding cap (252) is substantially recessed within the trench with respect to the top of the trench.

Abstract: A metal film forming method, includes the steps of (a) (s13, s15) supplying a plural kinds of ingredient gases to a base barrier film (3) in sequence, wherein at least one of the gases includes a metal, and (b) (s14, s16) vacuum-exhausting the ingredient gases of the step (a) or substituting the ingredient gases of the step (a) by an other kind of gas after the ingredient gases of the step (a) are supplied respectively, thereby an extremely thin film (5) of the metal is formed on the base barrier film (3).

Abstract: A ferroelectric memory device and a method for manufacturing the same. The ferroelectric memory device comprises a lower interlayer insulating layer formed on a semiconductor substrate. The ferroelectric memory device further comprises at least two adjacent ferroelectric capacitors disposed on the lower interlayer insulating layer, an interlayer insulation layer formed over the ferroelectric capacitors, leaving a top surface of the ferroelectric capacitors exposed, a patterned via etch-stop layer formed on the interlayer insulation layer, leaving the top surface of the capacitors exposed, an upper interlayer insulating layer formed on the patterned via etch-stop layer, and a plate line commonly connected to the at least two adjacent ferroelectric capacitors. Thus, integration of the ferroelectric memory device can be substantially increased.

Abstract: A method for controlling a plasma etch process while etching a layer stack having a first layer disposed above an end-point generating layer is disclosed. The method includes etching through the first layer and at least partially through the end-point generating layer while monitoring an absorption rate of a light beam traversing an interior portion of the plasma processing chamber, wherein the end-point generating layer is selected from a material that produces a detectable change in the absorption rate when etched. The end-point generating layer is characterized by at least one of a first characteristic and a second characteristic. The first characteristic is an insufficient thickness to function as an etch stop layer, and the second characteristic is an insufficient selectivity to etchants employed to etch through the first layer to function as the etch stop layer. The method additionally includes generating an end-point signal upon detecting the detectable change.