Abstract: A mirror-polished obverse surface and a roughened reverse surface of the conventional GaN wafers have been discriminated by difference of roughness on the surfaces with human eyesight. The difference of the surfaces is rather ambiguous. Cracks/breaks and distortion of the wafers have been likely to occur because the roughness of the reverse surface is apt to bring fine particles. To discern an obverse from a reverse without making use of the difference of the surface roughness, the present invention provides an obverse/reverse discriminative rectangular nitride semiconductor wafer having a longer slanting edge and a shorter slanting edge at obversely-clockwise neighboring corners, or having an asymmetric slanting edge at a corner, or having asymmetrically bevelled parts or having discriminating characters marked by laser. The present invention can make the reverse surface mirror-polished and smooth, so that particles on the reverse surface and distortion, cracks or breaks of the wafer decrease.

Abstract: Inducting devices having a patterned ground shield with ribbing in an integrated circuit. In one embodiment, an inducting device comprises conductive turns to conduct current, a shield layer and a plurality of ribs. The shield layer is formed a select distance from the conductive turns. The shield layer is patterned into sections of shield to prevent eddy currents. The plurality of ribs are formed from a conductive layer that is positioned between the conductive turns and shield layer. Each rib is electrically coupled to a single associated section of shield. Moreover, each rib is more conductive than its associated section of shield to provide a less resistive current path than its associated section of shield.

Abstract: A method for applying a passivation layer selectively on an exposed silicon surface from a liquid phase solution supersaturated in silicon dioxide. The immersion is conducted at substantially atmospheric temperature and pressure and achieves an effective passivation layer in an abbreviated immersion time, and without subsequent heat treatment. In one embodiment, rapid coating of a wafer back side with silicon dioxide permits the use of a high-speed electroless process for plating the bond pad with a solder-enhancing material. In another embodiment, the walls of via holes and microvia holes in a silicon body may be passivated by immersion in the supersaturated solution prior to plugging the holes with conductive material.

Abstract: A hetero-junction bipolar transistor that satisfies high resistance required to avoid a potential breakdown includes: an n-type sub-collector layer 110 that is made of GaAs; an n-type first collector 121 that is made of a semiconductor material with a smaller avalanche coefficient than that of the sub-collector 110 and is formed on the sub-collector layer 110; a second collector layer 132 that is made of n-type or i-type GaAs with lower dopant concentration than that of the sub-collector layer 110 and is formed on the first collector layer 121; a p-type base layer 133 that is made of GaAs and is formed on the second collector layer 132; and emitter layer 134 that is made of a semiconductor material with a larger band gap than that of the base layer 133 and is formed on the base layer 133.

Abstract: A method of electrically linking the contacts of a semiconductor device to their corresponding digit lines. The method includes disposing a quantity of mask material into a trench through which the contact is exposed. The mask also abuts a connect region of a conductive element of a corresponding digit line and, therefore, protrudes somewhat over a surface of the semiconductor device. A layer of insulative material is disposed over the semiconductor device with the mask material being exposed therethrough. The mask material is then removed, leaving open cavities that include the trench and a strap region continuous with the trench and with a connect region of the corresponding digit line. Conductive material is disposed within the cavity and electrically isolated from conductive material disposed in adjacent cavities, which define conductive plugs or studs and conductive straps from the conductive material.

Abstract: In a semiconductor device in which a plurality of field effect transistors are formed on a silicon surface having substantially a <110> orientation, the field effect transistors are disposed on the silicon surface such that a direction connecting a source region and a drain region of the field effect transistor is coincident to a substantially <110> direction.

Abstract: The method comprises forming a layer comprised of BPSG above a substrate and a plurality of transistors, forming a dielectric layer above the BPSG layer, the dielectric layer comprised of a material having a dielectric constant greater than approximately 6.0, forming a plurality of openings in the dielectric layer and the BPSG layer, each of the openings allowing contact to a doped region of one of the transistors, and forming a conductive local interconnect in each of the openings. In another embodiment, the method comprises forming a layer comprised of BPSG above the substrate and between the transistors, forming a local interconnect in openings formed in the BPSG layer, reducing a thickness of the BPSG layer after the local interconnects are formed, and forming a dielectric layer above the BPSG layer and between the local interconnects, wherein the dielectric layer has a dielectric constant greater than approximately 6.0.

Abstract: An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration. A control network can be used to control the biasing when the semiconductor devices are used in a series configuration.

Abstract: A semiconductor epitaxial structure includes a first semiconductor epitaxial layer and a second semiconductor epitaxial layer having a wider energy band gap than the first semiconductor epitaxial layer. The first semiconductor epitaxial layer includes a first sublayer of one conductive type and a second sublayer of the opposite conductive type. A pn junction is formed between the two sublayers. The semiconductor epitaxial structure may also include a third semiconductor epitaxial layer having a wider energy band gap than the first semiconductor epitaxial layer, the first semiconductor epitaxial layer being sandwiched between the second and third semiconductor epitaxial layers. This semiconductor epitaxial structure can be used in a semiconductor light-emitting device to obtain high emissive efficiency and an operating characteristic that remains linear into the high current injection region.

Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Abstract: A multi-chips package at least comprises a substrate, an upper chip, a lower chip, a reinforced device, and a plurality of electrically conductive bumps. The upper chip is flip-chip bonded to the upper surface of the substrate and the lower chip is accommodated in the opening and flip-chip bonded to the upper chip. Furthermore, the reinforced device is mounted onto the back surface of the lower chip and the lower surface of the substrate. The coefficient of the thermal expansion of the reinforced device ranges from the coefficient of the thermal expansion of the substrate to the coefficient of the thermal expansion of the chip. In such a manner, the reinforced device can constrain the thermal deformation of the substrate so as to prevent the electrically conductive bumps connecting the first chip and the substrate from being damaged.

Abstract: A method for fabricating a vertical integrated circuit is disclosed. Integrated circuits are fabricated on a substrate with layers of predetermined weak and strong bond regions where deconstructed layers of integrated circuits are fabricated at or on the weak bond regions. The layers are then peeled and subsequently bonded to produce a vertical integrated circuit. An arbitrary number of layers can be bonded and stacked in to a separate vertical integrated circuit. Also disclosed are methods of creating edge interconnects and vias through the substrate to form interconnections between layers and devices thereon.

Abstract: A semiconductor device of the present invention has an active region whose width varies. Gate electrodes cross over narrowest portions of the active region. Therefore, the device is not prone to producing leakage current even when the line width of the gate electrodes is small.

Abstract: A silane passivation process, carried out in-situ together with the formation of a subsequent dielectric film, converts the exposed Cu surfaces of a Cu interconnect structure, to copper silicide. The copper silicide suppresses Cu diffusion and electromigration and serves as a barrier material in regions where contact to further conductive material is made. An entire copper surface of a copper interconnect structure may be silicided or a local portion of the surface silicided after an opening is formed in an overlying dielectric to expose a portion of the copper surface.

Abstract: To provide a semiconductor device that is capable of reduction in thickness and high-density mounting, and that is simple in manufacturing process and convenient for use. A wiring substrate is formed with a plurality of opening portions. In each of the opening portions, a lower chip formed by a wafer-level chip size package (WCSP) is received, and an upper chip is placed on the lower chip. The composite including them is sealed by a sealing body such as epoxy resin. Internal connection terminals of each lower chip are electrically connected to pads of the corresponding upper chip via wirings, through holes and bonding posts of the wiring substrate, and wires.

Abstract: The present invention relates to a capacitive micro-electro-mechanical switch and method of manufacturing the same. In the capacitive micro-electro-mechanical switch for use in the radio frequency (RF) and the microwave driven by the electrostatic force, a capacitor of a 3-dimensional structure is formed on a signal transmission line. An ON capacitance is increased without increasing an capacitor area while preventing an increase in an OFF capacitance using the capacitor. Thus, an ON/OFF capacitance ratio of the capacitive micro-electro-mechanical switch can be increased and insertion loss and isolation characteristic could be improved.

Abstract: A semiconductor device with a package fixed to a case, comprising: a package where a semiconductor element and a lead terminal connected to the semiconductor element are sealed up; and a case formed by a frame member and an external terminal disposed to the frame member, characterized in that the package is located inside the frame of the case and the lead terminal is connected with the external terminal.

Abstract: Provided is a substrate identification circuit that generates a numeric value, whose duplication is difficult and which is proper to a substrate, at low cost and a semiconductor device having such a substrate identification circuit. A substrate identification circuit 304 is produced by utilizing variations in characteristics among TFTs formed on a substrate having an insulating surface. The substrate identification circuit 304 includes a plurality of proper bit generating circuits, each of which is constructed from a plurality of TFTs and outputs a one-bit random number based on variations in characteristics among the plurality of TFTs. The substrate identification circuit generates a numeric value proper to the substrate using the one-bit random number. The substrate identification circuit may include a circuit that makes a judgment by comparing the numeric value proper to the substrate with an identification number inputted from the outside.

Abstract: The present invention provides improved semiconductor wafer structures having isotopically-enriched layers and methods of making the same.

Abstract: A semiconductor device of the present invention has two inner inner leads to be bonded with inner-side bump electrodes each placed at a position which is a relatively large distance apart from the edge of a semiconductor chip, between outer-side bump electrodes each placed at a position which is a relatively small distance apart from the edge of the semiconductor chip. At least one of the inner inner leads is bent in accordance with a bonding position with the inner-side bump electrode.