Abstract: A data processing system includes a memory storing data to be retrieved and an I/O controller configured to request data stored in the memory at a plurality of addresses. The I/O may be responsive to an internal or external device requesting such data. A fetch machine provides or initiates retrieval of data stored at the requested address, while a prefetch machine predicts future requests and keeps track of memory requests already initiated and queued. Thus, the prefetch machine is responsive to the plurality addresses to predict others of the addresses and provide or initiate retrieval of data stored thereat. To avoid prefetching information already requested and in a fetch queue, the prefetch machine includes a memory storing a last one of the addresses subject to prefetching. Finally, to avoid conflicts between currently requested data and prefetch operation, an arbiter resolves memory accesses or data requests initiated by the fetch and prefetch machines.

Abstract: A cache is coupled to receive an access which includes a cache allocate indication. If the access is a miss in the cache, the cache either allocates a cache block storage location to store the cache block addressed by the access or does not allocate a cache block storage location in response to the cache allocate indication. In one implementation, the cache is coupled to an interconnect with one or more agents. In such an implementation, the cache accesses may be performed in response to transactions on the interconnect, and the transactions include the cache allocate indication. Thus, the source of a cache access specifies whether or not to allocate a cache block storage location in response to a miss by the cache access. The source may use a variety of mechanisms for generating the cache allocate indication.

Abstract: A storage management system in which a plurality of volume providers maps logical storage volumes onto one or more storage devices within a stand-alone computer or within a storage network. A common volume manager executing on a computer within the storage network selectively communicates commands to one or more of the volume providers in order to control the storage devices. The inventive storage management system seamlessly integrates management of the vendor-specific volume providers. The common volume manager provides a common application programming interface (API) by which applications are able to control and monitor hardware and software volume providers without requiring detailed knowledge of the volume providers or the underlying storage devices. The common volume manager aggregates response information from the volume providers and communicates the aggregated information to the software application that issued the storage management request.

Abstract: A behavioral memory mechanism for performing fetch prediction within a data processing system is disclosed. The data processing system includes a processor, a real memory, an address converter, a fetch prediction means, and an address translator. The real memory has multiple real address locations, and each of the real address locations is associated with a corresponding one of many virtual address locations. The virtual address locations are divided into two non-overlapping regions, namely, an architecturally visible virtual memory region and a behavioral virtual memory region. The address converter converts an effective address to an architecturally visible virtual address and a behavioral virtual address. The architecturally visible virtual address is utilized to access the architecturally visible virtual memory region of the virtual memory and the behavioral virtual address is utilized to access the behavioral virtual memory region of the virtual memory.

Abstract: A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.

Abstract: A method and system that enables independent burst lengths for reads and writes to a DRAM subsystem. Specifically, the method provides a mechanism by which read bursts may be longer than write bursts since there are statistically more reads than writes to the DRAM and only some beats of read data are modified and need to be re-written to memory. In the preferred embodiment, the differences in the burst length is controlled by an architected address tenure, i.e., a set of bits added to the read and write commands that specify the specific number of beats to read and/or write. The bits are set by the processor during generation of the read and write commands and prior to forwarding the commands to the memory controller for execution.

Abstract: A method of masking input data in a synchronous non-volatile flash memory. According to one embodiment of the present invention, a data mask connection is used to receive a mask signal. The mask signal forces at least a portion of input data having a programmed state to an erased state. In another embodiment, control circuitry is used to control write operations to memory cells of a memory array. In this embodiment, the control circuitry does not write input data having an erased state to the memory array.

Abstract: Striped mirrors are re-synchronized by logical partition rather than by stripe unit for stale partitions. While re-synchronizing physical partitions, data is serialized across both the stripe unit and the real partition region. The re-sync Read operation uses the normal logical partition offsets to read on a physical partition boundary rather than using the stripe units. In so doing, a single disk in a striped mirror can be replaced without re-synchronizing the entire mirror. The resync Read is not broken up into individual stripe unit reads.

Abstract: Memory corruption can be suppressed. When data stored in a random access area are read, the read data (physical block) are retrieved by a logic block number and newest data are read by referring to an incremental counter of data having that logic block number. When data are stored in the random access area, the incremental counter and the logic block number of data already stored in the random access area are referred and a physical block set to be unnecessary is set to a writer buffer, and then the data are written to this write buffer.

Abstract: A method and system for parallel fetch and decompression of compressed data blocks is disclosed. A method first accesses a table of pointers specifying the location of compressed data to obtain a pointer. Using the pointer, the method reads a pointer in the first block of data, the pointer specifying the location of the next block of compressed data in a chain of compressed data blocks. The method also transfers the rest of the first compressed data block to be decompressed. The method then fetches the next compressed data block using the second pointer while decompressing the first compressed data block. Using a pointer in each successive compressed data block in the chain, the method pre-fetches the next compressed data block while the previous compressed data block is being decompressed.

Abstract: The invention relates to a multiprocessor system having plural processors and an optical bus shared by the plural processors, and intends to simplify the cache control, reduce the volume of hardware, and shorten the memory access processing time. For this purpose, the multiprocessor system of the invention includes a shared memory, a cache memory connected to the shared memory, an optical bus connected to the cache memory, and plural processors connected to the optical bus, which access to the cache memory through the optical bus.

Abstract: A novel processor chip (10) having a processing core (12), at least one bank of memory (14), an I/O link (26) configured to communicate with other like processor chips or compatible I/O devices, a memory controller (20) in electrical communication with processing core (12) and memory (14), and a distributed shared memory controller (22) in electrical communication with memory controller (20) and I/O link (26). Distributed shared memory controller (22) is configured to control the exchange of data between processor chip (10) and the other processor chips or I/O devices. In addition, memory controller (20) is configured to receive memory requests from processing core (12) and distributed shared memory controller (22) and process the memory request with memory (14). Processor chip (10) may further comprise an external memory interface (24) in electrical communication with memory controller (20). External memory interface (24) is configured to connect processor chip (10) with external memory, such as DRAM.

Abstract: A data storage/transmission hardware device (or multiple devices physically linked together) with two (or more) access channels is disclosed. One of the access channels allows for reading and writing of information (referred to as the “active channel”) while the other access channel(s) (referred to as “passive channels”) allow solely for the reading of information. The actual limitation of “write” access of the passive access channels is brought about by a combination of hardware and firmware. The information stored/or transmitted through the device may be (but is not limited to) data such as digital, graphical, image, multi-media, stream or any other type of computing information. This methodology spans multiple media and computing device types.

Abstract: A circuit comprising a memory, a queue, and a translator. The memory may be configured to store a message at an address at least as great as a base address. The queue may be configured to store a descriptor, wherein the descriptor is configured to have (i) an index, (ii) a routing field, and (iii) fewer bits than the address. The translator may be configured to translate between the address and the index.

Abstract: The present invention relates to a method of producing a memory management table that controls memories having a function to hold data at a time of power cut-off and manages identifier information of memory areas which are data storage destinations designated by a logical address issued by a host device. After an initializing process, the host device is immediately notified of canceling of a busy state, without production of the memory management table. Alternatively, only a part of the memory management table is produced and the host device is notified of the canceling of the busy state. After that, until the host device issues a process request, or when the host device is issuing a process request, an incomplete part of the memory management table is completed. Thus, the memory management table can be completed.

Abstract: The invention concerns a method for protecting sensitive data against overflow in a stack, memory space reserved for part of a program. Said method comprises an operation which consists in assigning a stack to each program part, during which the most upstream stack relatively to the displacement direction of an indicator in a stack, is assigned a task for operating on said sensitive data. Preferably, said method comprises the execution of a single task operating on said sensitive data.

Abstract: The present invention is directed toward a system and method for caching data for multiple processes. The system utilizes a data storage device, and has at least one process adapted to utilize data stored in that data storage device. A component is used, which includes a basic set of instructions for creating and utilizing a memory map file in the data storage device. The memory map file stores data used by the process. A caching object is then built with the component. The caching object generates and manages the caching of data for the process in the memory map file. Also included in the present invention is a method for adding data caching ability to a process.

Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.

Abstract: A system and method is provided for executing both managed and unmanaged code in a managed environment and managing memory employing a garbage collection system or service. The code may be precompiled, compiled in real-time or interpreted. The system and method identify roots including object references and interior references on a stack. The object references and interior references are then reported to the garbage collection system or service. The garbage collection system or service employs both the object references and interior references when tracing the heap for objects and data members within the objects. Memory segments that are inaccessible are then reclaimed for assignment to other objects. The garbage collection system or service may be invoked periodically by an operating system, a memory manager or some other service. Alternatively, the garbage collection system can be invoked in response to a request for memory by an executing program.

Abstract: A cassette library (1) is provided with a driving apparatus (13), cassette housing shelves (14, 15) and a cassette carrier (16). A library controller (2) simulates as if driving apparatuses (13) having continuous address numbers were apparently used in the host computer (3) even when physically discontinuous address numbers are allocated to the driving apparatus (13), thereby making it possible to set occupancy for a driving apparatus with an arbitrary address number. The library controller (2) has the cassette carrier (16) automatically carry, at a preset timing, a cleaning cassette from the cassette housing shelf (14, 15) to the driving apparatus (13) to clean a recording reproduction head of the driving apparatus (13) using the cleaning cassette which is then carried back to the housing section in the original cassette housing shelf (14, 15) after the cleaning work.