Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.

Abstract: Methods, systems, and devices for automotive boot optimization are described. For instance, a memory system may record addresses that are accessed as part of multiple phases of a first boot-up procedure. During a second boot-up procedure, the memory system may transfer, from a logical block address of a non-volatile memory device to a volatile memory device, information for a respective phase based on the recording of the phases of the first boot-up procedure. The memory system may receive a command to transmit the information to a host system as part of the respective phase after transferring the information from the non-volatile device to the volatile memory device.

Abstract: A boot method for an embedded system is provided. The embedded system includes two mainboards each provided with a baseboard management controller (BMC), a non-volatile memory unit and a network adapter. When the embedded system is turned on, each of the BMCs performs a boot procedure, and then loads an operating system (OS) image file from a corresponding non-volatile memory unit to execute an operating system. When one BMC fails to load the OS image file or to execute the operating system, the BMC causes the corresponding network adapter to communicate with the other network adapter to acquire the OS image file from the non-volatile memory unit on the other mainboard, so as to replace the OS image file in the corresponding non-volatile memory unit, and directly loads the OS image thus acquired to execute the operating system.

Abstract: Methods, systems, and devices for data defragmentation for a system boot procedure are described. The memory system may determine a write random index associated with a boot procedure. The write random index may indicate a relationship between a first quantity of sequential logical addresses accessed as part of the boot procedure and a second quantity of random logical addresses accessed as part of the boot procedure. The memory system may determine whether the write random index satisfies a threshold based on determining the write random index. In some cases, the memory system may transfer, to a second portion of the memory system, data stored in a first portion of the memory system based on determining that the write random index satisfies the threshold. The memory system may receive a request to perform the boot procedure after transferring the data and output, to the host system, the data transferred.

Abstract: Waveform circuitry and related apparatuses and methods are disclosed. An apparatus includes a memory device to store waveform data corresponding to a waveform, a processor, and a waveform circuitry to autonomously pre-process the waveform data independently from the processor and provide the pre-processed waveform data to one or more peripheral devices. A pre-processed waveform corresponding to the pre-processed waveform is data different from the waveform.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more methods may: execute a first information handling system (IHS) initialization executable via an environment associated with IHS firmware; register, by the first IHS initialization executable, a process configured to store multiple IHS initialization executable/OS executable pairs via a volatile memory medium of the IHS; for each IHS initialization executable/OS executable pair of the multiple IHS initialization executable/OS executable pairs: call, by an IHS initialization executable of the IHS initialization executable/OS executable pair, the process; and copy, by the process, an OS executable of the IHS initialization executable/OS executable pair from the first non-volatile memory medium to the volatile memory medium; retrieve a driver via a network; execute the driver; and copy, by the driver, each OS executable, which was copied to the volatile memory medium, to a non-volatile memory medium of the IHS.

Abstract: A clustered storage system includes a plurality of storage devices, each of which contributes a portion of its memory to form a global cache of the clustered storage system that is accessible by the plurality of storage devices. Cache metadata for accessing the global cache may be organized in a multi-layered structure. In one embodiment, multi-layered structure has a first layer first including a first address array, and the first address array include addresses pointing to a plurality of second address arrays in a second layer. Each second address array in the second layer includes addresses, each of which points to data that has been cached in the global cache.

Abstract: A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

Abstract: A method of providing more efficient and streamlined data access to DRAM storage medium by all of multiple processors within a system on a chip (SoC) requires every processor to send use-of-bus request. When the request is for local access (that is, for access to that part of DRAM which is reserved for that processor), the processor reads or writes to the DRAM storage medium through its own arbitrator and own memory controller. When the request is for non-local access (that is, to DRAM within the storage medium which is reserved for another processor), the processor reads or writes to the “foreign” address in the storage medium through its own arbiter, its own memory controller, and its own DMA controller. A data access system is also disclosed.

Abstract: Systems, apparatuses, and methods related to image based media type selection are described. Memory systems can include multiple types of memory media (e.g., volatile and/or non-volatile). Determinations of which memory media types to write image data to can be made and the data can be written (e.g., stored) in the determined type of memory media. A determined memory media type can be based on attributes of the data. In an example, a method can include receiving, by a memory system that comprises a plurality of memory media types, initial image data from an image sensor coupled to the memory system, identifying one or more attributes of the initial image data, determining a type of memory media to write the initial image data to based on the identified attributes of the initial image data , and selecting, based at least in part on the determined type of memory media, a first memory type of the plurality of memory media types to write the initial image data.

Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

Abstract: A computer-implemented method according to one embodiment includes receiving, on a first cluster site, a first I/O request to migrate a plurality of filesets from a second cluster site to the first cluster site. The first cluster site includes a plurality of gateway nodes. The method further includes identifying at least two of the gateway nodes having resources available to perform operations of the migration, and hashing information of a plurality of filesets against the identified gateway nodes. The information includes inode numbers of entities that are mounted during fulfillment of the first I/O request. Operations of the first I/O request are distributed to the identified gateway nodes based on the hashing, and the identified gateway nodes are instructed to fulfill the operations.

Abstract: A medical system includes an input assembly for receiving one or more user inputs. The input assembly includes at least one slider assembly for providing an input signal. Processing logic receives the input signal from the input assembly and provides a first output signal and a second output signal. A display assembly is configured to receive, at least in part, the first output signal from the processing logic and render information viewable by the user. The second output signal is provided to one or more medical system components. The information rendered on the display assembly may be manipulatable by the user and at least a portion of the information rendered may be magnified.

Abstract: A content provider system includes: a repository to store a catalog of content; a storage device pool to load content from among the catalog of content from the repository into one or more storage devices of the storage device pool; a first hosted device communicably connected to the storage device pool, and to execute the content stored in the storage device pool to provide the content to a first user device; a second hosted device communicably connected to the storage device pool, and to execute the content stored in the storage device pool to provide the content to a second user device; and one or more processing circuits to identify an available storage device from among the one or more storage devices of the storage device pool for serving a requested content to a requesting device from among the first and second hosted devices.

Abstract: An adaptive interface storage device. In some embodiments, the adaptive interface storage device includes: a rear storage interface connector; an adaptable circuit connected to the rear storage interface connector; a first multiplexer, connected to the adaptable circuit; and a front storage interface connector, connected to the first multiplexer. The adaptive interface storage device may be configured to operate in a first state or in a second state. The adaptive interface storage device may be configured: in the first state, to present a device side storage interface according to a first storage protocol at the front storage interface connector, and in the second state, to present a device side storage interface according to a second storage protocol, different from the first storage protocol, at the front storage interface connector.

Abstract: A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

Abstract: A method is implemented by a system on chip and includes: receiving a volume attaching request sent by the public cloud management component, where the volume attaching request includes an identifier of a system volume; and storing the identifier of the system volume based on the volume attaching request, where when the bare-metal server is started, the bare-metal server uses the identifier of the system volume to determine the system volume, and starts an operating system of the bare-metal server based on the system volume, and the system volume stores a file used for starting the operating system of the bare-metal server.

Abstract: A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n?1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.

Abstract: A plug-in mobile peripheral component interconnect express module connector is disclosed, comprising a plastic body, and a first terminal set and a second terminal set disposed relatively in the plastic body. The plastic body includes transversely penetrated slots, an upper end surface of the slots has intermittently plural upper magazines, and a lower end surface has intermittently plural lower magazines. The first terminal set includes plural first elastic terminals inserted in the upper magazines, and the second terminal set includes plural second elastic terminals inserted in the lower magazines. Each first elastic terminal is opposed to each second elastic terminal, forming a holding gap. A motherboard is inserted between the first elastic terminals and the second elastic terminals from a side, and an MXM board is inserted between the first elastic terminals and the second elastic terminals from the other side.

Abstract: Techniques facilitating write-only device state inferences. In one example, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise: a monitor component; and a state component. The monitor component can compare a property of a feedback signal output by a write-only device with a reference signal. The state component can determine a state of the write-only device based on a comparison between the property and the reference signal.