Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.
Abstract: A chassis front-end is disclosed. The chassis front-end may include a switchboard including an Ethernet switch, a Baseboard Management Controller, and a mid-plane connector. The chassis front-end may also include a mid-plane including at least one storage device connector and a speed logic to inform at least one storage device of an Ethernet speed of the chassis front-end. The Ethernet speeds may vary.
Abstract: Disclosed herein are systems, methods, and apparatuses where a controller can automatically manage a physical infrastructure of a computer system based on a plurality of system rules, a system state for the computer system, and a plurality of templates. Techniques for automatically adding resources such as computer, storage, and/or networking resources to the computer system are described. Also described are techniques for automatically deploying applications and services on such resources. These techniques provide a scalable computer system that can serve as a turnkey scalable private cloud.
Type:
Grant
Filed:
December 22, 2021
Date of Patent:
December 20, 2022
Assignee:
Net-Thunder, LLC
Inventors:
Parker John Schmitt, Sean Michael Richardson, Neil Benjamin Semmel, Cameron Tyler Spry
Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.
Type:
Grant
Filed:
December 17, 2019
Date of Patent:
December 13, 2022
Assignee:
Apple Inc.
Inventors:
Robert E. Jeter, Rakesh L. Notani, Alma L. Juarez Dominguez
Abstract: A storage device for booting a host computing device includes a first storage memory region having a first storage memory controller, a second storage memory region having a second storage memory controller, and a resilient boot controller. The resilient boot controller is configured to store boot code in the first storage memory region, prevent write access by the host computing device through the first storage memory controller to the first storage memory region, detect a reset of the host computing device through the input/output interface, copy at least a portion of the boot code from the first storage memory region to the second storage memory region, responsive to detection of the reset of the host computing device, and enable read access of the copied boot code by the host computing device through the second storage memory controller of the second storage memory region, responsive to the copy operation.
Type:
Grant
Filed:
April 20, 2020
Date of Patent:
December 6, 2022
Assignee:
Microsoft Technology Licensing, LLC
Inventors:
Stefan Thom, Paul England, Robert Karl Spiger, Brian Telfer, Sangho Lee, Marcus Peinado
Abstract: A controller is included in a storage device communicating with a host device. The controller is configured to receive a firmware image download command and a firmware image corresponding to the firmware image download command from the host device, perform verification for determining whether the firmware image is damaged in response to the received firmware image download command, and when a firmware update request for the firmware image is received from the host device, determine whether to perform a firmware update based on the firmware image by using a verification result of the firmware image.
Type:
Grant
Filed:
March 11, 2021
Date of Patent:
December 6, 2022
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Soohwan Kang, Jaesub Kim, Jeongbeom Seo
Abstract: A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.
Type:
Grant
Filed:
July 20, 2020
Date of Patent:
December 6, 2022
Assignees:
STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS APPLICATION GMBH
Abstract: To improve data throughput and data transfer rate, a contiguous block of host memory can be allocated for data transfers between the host system and an integrated circuit device such as a peripheral component. By using a contiguous block of memory that acts as a circular buffer, the memory address field of memory descriptors can be eliminated because the host system only need to inform the data movement engine of the length of each data transfer. The data movement engine can maintain pointers to keep track of the memory address in the host memory to read from and write to. After each data transfer, the relevant pointer can be incremented by a value corresponding to the length indicated in the memory descriptor for the transfer. As such, it is not necessary for the host system to provide the data movement engine with the memory address of each transfer.
Abstract: An apparatus comprising: at least one electrode, having a first potential, arranged to sense a biosignal; a conductive shield provided over the at least one electrode where the conductive shield is configured to be driven to a second potential wherein the second potential is equivalent to the first potential plus a multiple of an inverted common mode voltage; and wherein the conductive shield is coupled to a drain to enable triboelectric charges to be dissipated.
Abstract: The present application provides a method for storing an image frame in a memory, including: receiving the image frame; dividing the image frame into M rows of data block rows along a first direction; dividing each of the M rows of data block rows into N data blocks along a second direction perpendicular to the first direction; performing a compression operation upon each of the M*N data blocks individually to generate M*N compressed data blocks; and storing N compressed data blocks corresponding to the 1st data block row of the M data block rows and N compressed data blocks corresponding to the (P+1)th data block row of the M data block rows in a continuous storage space in the memory, wherein M, N, and P are integers, and M>1, N>0 and P<M.
Abstract: A system is provided to receive a request to write data to a storage device, wherein the data is associated with a file name and a file path. The system performs a hash function on an input based on the file name and the file path to obtain a hash value, wherein the hash function comprises a plurality of hash methods performed on the input. The system maps the hash value to a physical location in the storage device, and writes the data to the physical location in the storage device.
Abstract: A device may include a number of drivers, wherein each driver of the number of drivers includes a number of transistors coupled to an output node. The device may further include circuitry coupled to the number of drivers. The circuitry may configure at least one driver of the number of drivers in each of a number of configurations, wherein each configuration of the number of configurations is associated with a calibration code of a number of calibration codes. Each configuration generates, in response to signal transmission via the output node, an associated channel performance response of a number of channel performance responses. The circuitry may also store a calibration code for the at least one unit driver, wherein the calibration code generates a desired channel performance response of the number of channel performance responses. Systems and related methods of operation are also described.
Abstract: A methodology to track patient usage of an autoinjector (AI) device, and to an external or electronic adaptor (eAdaptor) adapted to be used with the AI are disclosed. The eAdaptor contains sensors (including but not limited to a temperature sensor, a sound sensor, a vibration sensor and a magnetic sensor system), a display, a microprocessor, a real time clock, and communication systems that enables the eAdaptor to capture and confirm autoinjector (AI) use, as well as injection information, and transmit such information wirelessly to a smart phone or any other data receiving system or device. Also disclosed are an internal logic to operate the eAdaptor and a smart device APP that pairs with the internal logic to guide the patients with graphical user interface (GUI) displays on the smart device.
Type:
Grant
Filed:
August 9, 2018
Date of Patent:
October 25, 2022
Assignee:
MEDIMMUNE, LLC
Inventors:
Michael C. Song, Janardhanan Anand Subramony
Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.
Abstract: Methods and systems for utilizing co-simulation of a physical model and a self-adaptive predictive controller using hybrid automata are described. For example, there is disclosed a self-adaptive predictive control system to generate an initial patient model with initial patient model settings (k1, k2, . . . , kn) and execute a program that takes as input, the initial patient model settings as configuration parameters that specify at least a plurality of initial states. Such a system further receives new patient inputs and generates hybrid automata as a variation of the initial states by applying the new patient inputs to the initial patient model. The system further derives reachable states from the hybrid automata and outputs all reachable states computed. The system further detects changes and responsively generates a new patient predictive model with new parameter settings (k?1, k?2, . . . , k?n), iteratively repeating until a termination criterion is satisfied. Other related embodiments are disclosed.
Type:
Grant
Filed:
October 4, 2019
Date of Patent:
October 18, 2022
Assignee:
Arizona Board of Regents on behalf of Arizona State University
Abstract: To provide an elevator car position detection sensor capable of suppressing erroneous detection of presence or absence of a plate. The elevator car position detection sensor includes a first coil provided to one of an elevator car and a hoistway and configured to output an excitation magnetic field to a plate provided to the other of the elevator car and the hoistway; a second coil provided on an opposite side of the first coil relative to the plate; a shield wall configured to shield an end portion of the plate located closer to one of the car and the hoistway; and a determination circuit configured to determine a phase of an alternating-current voltage corresponding to a frequency of the excitation magnetic field output from the first coil at an alternating-current voltage generated across the second coil.
Type:
Grant
Filed:
May 10, 2017
Date of Patent:
October 18, 2022
Assignee:
MITSUBISHI ELECTRIC CORPORATION
Inventors:
Jin Inoue, Keita Mochizuki, Masahiro Ishikawa, Akihide Shiratsuki
Abstract: A chassis front-end is disclosed. The chassis front-end may include a switchboard including an Ethernet switch, a Baseboard Management Controller, and a mid-plane connector. The chassis front-end may also include a mid-plane including at least one storage device connector and a speed logic to inform at least one storage device of an Ethernet speed of the chassis front-end. The Ethernet speeds may vary.
Abstract: Mechanisms for managing output of an HDMI source are provided. In accordance with some implementations of the disclosed subject matter, a method for controlling output of an HDMI source is provided, the method comprising: establishing a connection between the HDMI source and an HDMI sink at a first address of a consumer electronic control bus of the HDMI sink; sending a request for an identity of the active source connected to the HDMI sink; monitoring signals on the consumer electronic control bus; receiving a message over the consumer electronic control bus identifying a second address on the consumer electronic control bus different from the first address as an address of an active source; setting a status of the HDMI source as inactive in response to receiving the message; and inhibiting output of video from the HDMI source to the HDMI sink in response to the status being set as inactive.
Abstract: A processing device receives a command to arm a memory device for self-destruction. In response to the command, a self-destruction countdown timer is commenced. An expiry of the self-destruction countdown timer and based on detecting the expiry of the self-destruction countdown timer, data stored by the memory device is destructed.
Abstract: Methods and systems for operating an I/O system are disclosed. Embodiments of the present technology may include a method that involves receiving data at a NIC, caching the data at the NIC, generating a meta-identifier (meta-ID) for the data, writing the data to a host via a PCIe interface, providing the meta-ID to the host, receiving a request for a service at the NIC from the host, the request including the meta-ID, accessing the cached data in the NIC using the meta-ID, and performing the service on the cached data that was accessed in the NIC using the meta-ID.