Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract: An organic electroluminescent display device includes a first substrate, a second substrate spaced apart and facing the first substrate, a switching thin film transistor disposed on an inner surface of the first substrate, a driving thin film transistor electrically connected to the switching thin film transistor, a connecting electrode electrically connected to the driving thin film transistor, a first electrode disposed on an inner surface of the second substrate, a partition wall disposed on the first electrode and having a transmissive hole corresponding to a pixel region between the first and second substrates, an organic layer disposed within the transmissive hole on the first electrode, and a second electrode disposed on the organic layer, wherein the second electrode is electrically connected to the driving thin film transistor through the connecting electrode.

Abstract: The light-emitting device includes a light source and a gradient index (GRIN) element. The GRIN element has a cylindrical refractive index profile in which the refractive index varies radially and is substantially constant axially. The GRIN element includes a first end surface opposite a second end surface and is characterized by a length-to-pitch ratio. The GRIN element is arranged with the first end surface adjacent the light source to receive light from the light source, and emits the light from the second end surface in a radiation pattern dependent on the length-to-pitch ratio. Since the radiation pattern depends on the length-to-pitch ratio of the GRIN element, LEDs with different radiation patterns can be made simply by using GRIN elements of appropriate lengths.

Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

Abstract: The improved light-emitting device may include a waveguide made with Si nanocrystals doped with optically active elements. The improved light-emitting device may be suitable for use in chip-to-chip and on-chip interconnections.

Abstract: An LSI device includes a core region to which a first driving voltage is applied and an interface region to which a second driving voltage higher than the above first driving voltage is applied. The LSI device includes an SOI substrate and a device separation region for separating a SOI layer of the SOI substrate into the core region and the interface region. The thickness of the SOI layer of the core region is thinner than the thickness of the SOI layer of the interface region. The LSI device further includes first MOSFETs formed in the core region and in which the SOI layer of the core region is a fully depleted Si channel and second MOSFETs formed in the interface region and in which the SOI layer of the interface region is a fully depleted Si channel.

Abstract: A semiconductor integrated circuit including a plurality of bipolar transistors that are produced by forming, in a plurality of transistor-producing regions, a first conductive type emitter layer on the front surface side of a second conductive type base layer that is formed on the surface side of a first conductive collector layer and contains germanium, the first conductive type emitter layer being formed from a semiconductor material having a band gap larger than the base layer. The concentrations of impurities contained in the emitter layers vary among the plurality of transistor-producing regions, and the germanium concentrations differ in the base-emitter junction interfaces of at least two of the transistor-producing regions, such that the ON-state voltages required for turning the plurality of bipolar transistors into an ON state differ from each other.

Abstract: A semiconductor apparatus includes lower conductive film strips, an inter-layer insulating layer, implanted conductive members, and upper conductive film strips. The lower conductive film strips are formed in a pattern closely adjacent in a line width orientation, electrically separated from each other. The inter-layer insulating layer is formed the lower conductive film strips. The implanted conductive members are implanted in connection holes formed in the inter-layer insulating layer at positions corresponding to both edge sides of the lower conductive film strips. The upper conductive film strips are formed on the implanted conductive members and the inter-layer insulating layer to connect the lower conductive film strips in series so that the lower conductive film strips, the implanted conductive members, and the upper conductive film strips form an electric coil.

Abstract: Methods are provided for selective formation of oxidation-resistant caps for conductive plugs in semiconductor device fabrication. One embodiment of the present invention forms a sacrificial layer over a recessed polysilicon plug. The sacrificial layer is readily planarized using chemical mechanical planarization to isolate the cap within a recessed via. Then, an immersion plating process is used to replace the atoms of the sacrificial layer with atoms of a desired metal, such as platinum, thereby creating a metal cap isolated within the via. The advantages of planarization to isolate material within recessed via are thus obtained without having to planarize or otherwise etch the desired metal. The cap layer can be further reacted to form a barrier compound prior to forming a capacitor over the plug. Advantageously, the plug structure resists oxidation during fabrication of overlying capacitors that incorporate high dielectric constant materials.

Abstract: A test pattern (100, 200, 300, 400, 600, 700) has a first metal structure (102) disposed on a substrate (352), one or more intermediate layers (358) disposed above the first metal structure (102) and a second metal structure (104) disposed above the one or more intermediate layers (352). A first via (106) passes through the intermediate layers (352) and connects the first metal structure (102) to the second metal structure (104). One or more third metal structures (108) are disposed above the one or more intermediate layers (352) and the first metal structure (102). One or more second vias (110) pass through the intermediate layers (352) and connect the first metal structure (102) to the third metal structures (108). The second vias (110) are located outside of a radius (R) from a center of the first via (106). The third metal structures (110) are separated from the second metal structure (104) by a dielectric material (366).

Abstract: A semiconductor device can be manufactured which has a low resistance, and device characteristics of which do not vary. The semiconductor device includes a silicon layer, a gate dielectric film formed on the silicon layer, a gate electrode formed on the gate dielectric film and including a nitrided metal silicide layer which is partially crystallized, and source and drain regions formed in a surface region of the silicon layer at both sides of the gate electrode.

Abstract: A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other via a capacitive insulating layer made of a ferroelectric material. The storage node electrode has a surface covered with the capacitive insulating layer and is formed in a shape of column on one of the pair of impurity diffusion layers in a hole formed from an inter-layer insulating film covering the access transistor to the one of the pair of impurity diffusion layers. A upper surface of the column does not exceed the inter-layer insulating film. The storage node electrode formed in the hole face the cell plate electrode via the inter-layer insulating film.

Abstract: The present invention is a modified darlington phototransistor wherein a phototransistor is coupled to a Bipolar Junction Transistor (BJT). This design provides a high sensitivity and a fast response and effectively increases the gain of the photocurrent. This circuit is particularly will suited for the readily available CMOS and Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) processes prevalent today.

Abstract: An ultra-high density data storage device using phase-change diode memory cells, and having a plurality of emitters for directing beams of directed energy, a layer for forming multiple data storage cells and a layered diode structure for detecting a memory or data state of the storage cells, wherein the device comprises a phase-change data storage layer capable of changing states in response to the beams from the emitters, comprising a material containing copper, indium and selenium. A method of forming a diode structure for a phase-change data storage array, having multiple thin film layers adapted to form a plurality of data storage cell diodes, wherein the method comprises depositing a first diode layer of material on a substrate, and depositing a second diode layer of phase-change material on the first diode layer, the phase-change material containing copper, indium and selenium.

Abstract: A semiconductor integrated circuit device, and method of manufacturing the same, includes an inductor with improved inductance and an improved quality factor (Q-factor) that can be miniaturized. In one example, an inductor (3) is provided on an insulating layer (2) of a multilayer interconnection layer (1). The inductor (3) is formed by a spiral arrangement of a wiring (3a). A lamination film (14) is provided in an internal region (13) of an inductor (3) on insulating layer (2), and can be formed by laminating a titanium-tungsten (TiW) layer (9), a copper (Cu) layer (10), a ferromagnetic substance layer (15) made of nickel (Ni), a Cu layer (11), and a TiW layer (12), in that order. A lower surface of ferromagnetic substance layer (15) can be lower than an upper surface of wiring layer (3a), and an upper surface of ferromagnetic substance layer (15) can be higher than a lower surface of wiring layer (3a).

Abstract: A memory cell of a stacked type is formed by a MOS transistor and a ferroelectric capacitor. The MOS transistor is formed in an active region of a substrate of semiconductor material and comprises a conductive region. The ferroelectric capacitor is formed on top of the active region and comprises a first and a second electrodes separated by a ferroelectric region. A contact region connects the conductive region of the MOS transistor to the first electrode of the ferroelectric capacitor. The ferroelectric capacitor has a non-planar structure, formed by a horizontal portion and two side portions extending transversely to, and in direct electrical contact with, the horizontal portion.

Abstract: In a method of manufacturing a semiconductor device, a device including gate electrodes and asymmetric source and drain regions is formed by employing a semiconductor layer structure. The short channel effect is prevented in the resulting device even though the gate electrodes are of a dimension on the order of nanometers. Additionally, the gate electrodes and asymmetric source and drain regions of the semiconductor device may be precisely formed to have dimensions on the nanometer scale because a semiconductor layer structure is used in the process for manufacturing the semiconductor device.

Abstract: According to the present invention, there is provided a new GaN-based field effect transistor of a normally-off type, which has an extremely small ON resistance during operation and is capable of a large-current operation.

Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film.

Abstract: In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. A data line-word line imbalance generates large noise when the data lines are subjected to amplification, which is highly likely to invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.