Abstract: The nitride semiconductor device according to one embodiment of the present invention comprises: a silicon substrate; a first aluminum gallium nitride (AlxGa1?xN (0?x?1)) layer formed as a channel layer on the silicon substrate in an island shape; and a second aluminum gallium nitride (AlyGa1?yN (0?y?1, x<y)) layer formed as a barrier layer of a first conductive type or i-type on the first aluminum gallium nitride layer.

Abstract: A driving circuit and a data-line driver is provided which are capable of improving the tolerance to noise between adjacent terminals by using a conventional CMOS process while keeping the chip size small, because a high-density N-diffusion layer (116) is provided in an isolation region (115) to minimize a collector current of a parasitic NPN transistor (102).

Abstract: A solid state image sensing device is composed of a second conductive type well area 33, a photoelectric conversion area 40, a ring shaped gate electrode 35, a transfer gate electrode 41, a second conductive type drain area 38, a second conductive type source area 36, and a first conductive type source neighborhood area 37.

Abstract: In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions protrude above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric (164) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (160).

Abstract: A III–V group nitride system semiconductor self-standing substrate has: a first III–V group nitride system semiconductor crystal layer that has a region with dislocation lines gathered densely, the dislocation lines being gathered substantially perpendicular to a surface of the substrate, and a region with dislocation lines gathered thinly; and a second III–V group nitride system semiconductor crystal layer that is formed up to 10 ?m from the surface of the substrate on the first III–V group nitride system semiconductor crystal layer and that has a dislocation density distribution that is substantially uniform.

Abstract: A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. At least a portion of the semiconductor device may be exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. The alignment device may secure the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.

Abstract: A sensor device includes a sensor chip and a bonding wire being fixed on a substrate. The sensor device is manufactured by using a binding material made of an adhesive containing a foaming agent that evaporates upon exposure to heat. The binding material reduces its elasticity after a wire bonding process because voids being functional as a cushion are formed by evaporation of the foaming agent.

Abstract: A pad oxide film and a silicon nitride film are formed on a semiconductor substrate. Next, after the patterning of the silicon nitride film, by etching the pad oxide film and the substrate, a first trench is formed in a first region and a second trench is formed in a second region. After that, by performing side etching of the pad oxide film of the first region while protecting the second region with a resist, a gap is formed between the substrate and the silicon nitride film. Subsequently, the inner surfaces of the first and second trenches are oxidized. At this time, a relatively large volume of oxidizing agent (oxygen) is supplied to a top edge portion of the first trench, and the curvature of the corner of the substrate increases.

Abstract: Includes a stem with a hole, a dielectric sealed into the hole of the stem and including a pair of pin insertion holes, and a pair of high frequency signal pins that penetrate and fit into the pair of pin insertion holes of the dielectric, and constituting differential lines connected to an optical semiconductor element.

Abstract: An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).

Abstract: According to one embodiment a microelectromechanical (MEMS) switch is disclosed. The MEMS switch includes a top movable electrode, and an actutaion electrode with an undoped polysilicon stopper region to contact the top movable electrode when an actuation current is applied. The undoped polysilicon stopper region prevents actuation charging that accumulates over time in a unipolar actuation condition.

Abstract: A memory cell device includes a first electrode, phase-change material adjacent the first electrode, a second electrode adjacent the phase-change material, a diffusion barrier adjacent the phase-change material, and isolation material adjacent the diffusion barrier for thermally isolating the phase-change material. The diffusion barrier prevents diffusion of the phase-change material into the isolation material.

Abstract: In the case of the semiconductor component (1) according to the invention, the source regions (S), the body regions (B) and, if appropriate, the body contact regions (Bk) are in each case arranged in mesa regions (M) of adjacent trenches (30). In the edge region (R) of the cell array (Z) the insulation (GOX, FOX) of the underlying trench structures (30) by an insulating oxide layer (FOX) is comparatively thick and formed in the form of a field oxide (FOX) or thick oxide (FOX).

Abstract: In consideration of an optimum combination of impurities used for the purpose of forming an extension region (13) and a pocket region (11) and further inhibiting impurity diffusion in the extension region (13) when an impurity diffusion layer (21) is formed in a semiconductor device having an nMOS structure, at least phosphorus (P) is used as an impurity in the extension region (13), at least indium (In) is used as an impurity in the pocket region (11), and additionally carbon (C) is used as a diffusion inhibiting substance. Consequently, it is possible to easily and surely realize the scaling down/high integration of elements while improving threshold voltage roll-off characteristics and current drive capability and reducing a drain leakage current especially in the semiconductor device having the nMOS structure, and particularly by making the optimum design of a semiconductor device having a CMOS structure possible, improve device performance and reduce power consumption.

Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

Abstract: An IC package substrate having integral ESD protection features and elements and a method for construction of the same are disclosed

Abstract: A voltage booster transistor with an optimal conducting path formed in widebandgap semiconductors like Silicon Carbide and Diamond, is provided as a power transistor with a voltage rating >200V. Contrary to conventional vertical design of power transistors, a higher, optimum doping for a given thickness supports higher Source/Drain blocking voltage. A topside and backside gate region of the opposite conductivity type than the channel region providing control of source to drain current path through a small gate voltage. The backside gate and the Drain junction are able to support the rated blocking voltage of the device.

Abstract: A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high concentration Si body region, an n? Si region, a SiGe channel region containing n-type low concentration impurities, an n-type low concentration Si cap layer, and a contact which is a conductor member for electrically connecting the gate electrode and the Si body region. The present invention extends the operation range while keeping the threshold voltage small by using, for the channel layer, a material having a smaller potential at the band edge where carriers travel than that of a material constituting the body region.

Abstract: A group 3–5 compound semiconductor comprising an interface of two layers having lattice mismatch, an intermediate layer having a film thickness of 25 nm or more and a quantum well layer, in this order. The compound semiconductor has high crystallinity and high quality, and suitably used for a light emitting diode.

Abstract: Briefly, in accordance with an embodiment of the invention, a phase change memory and a method to manufacture a phase change memory is provided. The phase change memory may include a memory material and a first tapered contact adjacent to the memory material. The phase change memory may further include a second tapered contact separated from the first tapered contact and adjacent to the memory material, wherein the first and second tapered contacts are adapted to provide a signal to the memory material.