Abstract: A semiconductor structure includes a semiconductor substrate and a gate structure embedded in the semiconductor substrate. The gate structure includes a gate electrode layer, a barrier layer disposed over the gate electrode layer, and a semiconductor layer disposed over the barrier layer. The semiconductor structure also includes an air gap in the semiconductor substrate and exposing the barrier layer and the semiconductor layer.

Abstract: A copper pillar bump structure on a copper pillar on a metal pad of a semiconductor device and a method of fabricating thereof are disclosed. The copper pillar bump structure includes: a metal barrier layer formed on the copper pillar. The metal barrier layer has a U-shaped cross section, a central portion of the metal barrier layer covers the top surface of the copper pillar, an opening of the U-shaped cross section faces away from the copper pillar. The copper pillar bump structure further includes a solder layer on the copper pillar and filling the U-shaped cross section. The copper pillar bump structure provides a metal barrier layer having a U-shaped cross section and fills a solder layer in the U-shaped cross section, the metal barrier layer wraps sides of the solder layer, which can improve the non-wetting problem caused by insufficient tin, or the solder bridging problem caused by excessive solder, during a flip die soldering process.

Abstract: A semiconductor package includes: a first semiconductor device including a first pad and a first metal bump structure on the first pad; and a second semiconductor device on the first semiconductor device, and including a third pad and a second metal bump structure on the third pad, wherein the first and second metal bump structures are bonded to each other to electrically connect the first and second semiconductor devices to each other. Each of the first and second metal bumps structures includes first to third metal patterns. The first to third metal patterns of the first metal bump structure are on the first pad. The first to third metal patterns of the second metal bump structure are on the third pad. The first and third metal patterns include a first metal having a first coefficient of thermal expansion less than that of a second metal of the second metal pattern.

Abstract: A semiconductor package comprises a substrate; an interposer on the substrate; a first underfill between the substrate and the interposer; at least one logic chip and at least one memory stack on the interposer; and a molding material on the interposer while surrounding a side surface of the at least one logic chip and a side surface of the at least one memory stack. The molding material includes areas having different heights. The first underfill covers a portion of the molding material.

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern, a lower dielectric layer that covers a sidewall of the under-bump pattern, and a first redistribution pattern on the lower dielectric layer. The first redistribution pattern includes a first line part. A width at a top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern. A thickness of the under-bump pattern is greater than a thickness of the first line part.

Abstract: A semiconductor module includes a substrate having a central region, an outer region that surrounds the central region, and a middle region disposed between the central and the outer region, a first semiconductor package mounted on the central region of the substrate, a plurality of second semiconductor packages mounted on the middle region of the substrate, and a heat radiation structure disposed on the first semiconductor package and second semiconductor packages. The heat radiation structure includes a first part that is disposed on top surfaces of the first and second semiconductor packages, a second part that surrounds the middle region, a third part that is spaced apart from the second part and surrounds the first semiconductor package, and a fourth part that connects the second part to the third part.

Abstract: Disclosed is a method for designing an integrated circuit, wherein the integrated circuit is to be structured in cells, wherein the cells are to comprise functional cells and spare cells. The method comprises: a) designing at least one functional cell; and b) placing a plurality of functional cells on associated pattern positions of an, in particular regular, pattern matrix designed for the functional cells. The method further comprises c) placing, on at least one of the remaining pattern positions of the pattern matrix and instead of at least one spare cell conceivable for the at least one of the remaining pattern positions of the pattern matrix, a gate-based decoupling cell, and alternatively or in addition, d) placing, in at least one gap between pattern positions of the matrix pattern and instead of at least one filler cell conceivable for the at least one gap between pattern positions of the pattern matrix, a gate-based decoupling cell.

Abstract: A glass core device with a wiring pattern on a first surface of a glass core and a wiring pattern on a second surface thereof being electrically connected via a wiring pattern embedded in TGVs formed in the glass core. In a state of being cut out by dicing, each glass core has a second surface and side faces which are continuously covered with an outer protective layer.

Abstract: An object of the present disclosure is to suppress variation in currents flowing through semiconductor elements and thereby to achieve size reduction of the semiconductor elements. The semiconductor power module includes electrode terminals for connecting a first electrode to a first external electric component, a second electrode joined to upper surfaces of a plurality of semiconductor elements, and a second electrode extension portion for connecting the second electrode to a second external electric component. The sum of a current path length from the electrode terminal to the semiconductor element in the first electrode and a current path length from the semiconductor element to a second electrode terminal portion in the second electrode, is set to be the same among the plurality of semiconductor elements.

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

Abstract: A System in Package, SiP semiconductor device includes a substrate of laser direct structuring, LDS, material. First and second semiconductor die are arranged at a first and a second leadframe structure at opposite surfaces of the substrate of LDS material. Package LDS material is molded onto the second surface of the substrate of LDS material. The first semiconductor die and the package LDS material lie on opposite sides of the substrate of LDS material. A set of electrical contact formations are at a surface of the package molding material opposite the substrate of LDS material. The leadframe structures include laser beam processed LDS material. The substrate of LDS material and the package LDS material include laser beam processed LDS material forming at least one electrically-conductive via providing at least a portion of an electrically-conductive line between the first semiconductor die and an electrical contact formation at the surface of the package molding material opposite the substrate.

Abstract: A wafer level chip scale package (WLCSP) with portions that have different thicknesses. A first passive surface of a die in the WLSCP includes a plurality of surfaces. The plurality of surfaces may include inclined surfaces or flat surfaces. Thicker portions of die, with more semiconductor material remaining are non-critical portions that increase a WLCSP's strength for further processing and handling after formation, and the thinner portions are critical portions that reduce a Coefficient of Thermal Expansion (CTE) mismatch between a WLCSP and a PCB.

Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a metal sintered material such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.

Abstract: An integrated circuit structure comprises a first and second conductive structures formed in an interlayer dielectric (ILD) of a metallization stack over a substrate. The first conductive structure comprises a first conductive line, and first dummy structures located adjacent to one or more sides of the first conductive line, wherein the first dummy structures comprise respective arrays of dielectric core segments having a Young's modulus larger than the Young's modulus of the ILD, the dielectric core segments being approximately 1-3 microns in width and spaced apart by approximately 1-3 microns. The second conductive structure formed in the ILD comprises a conductive surface and second dummy structures formed in the conductive surface, where the second dummy structures comprising an array of conductive pillars.

Abstract: A semiconductor package includes a semiconductor chip including a contact pad on an active surface, a first insulating layer on the active surface including a first opening that exposes the contact pad, a redistribution layer connected to the contact pad and extending to an upper surface of the first insulating layer, a second insulating layer on the first insulating layer and including a second opening that exposes a contact region of the redistribution layer, a conductive post on the contact region, an encapsulation layer on the second insulating layer and surrounding the conductive post, and a conductive bump on an upper surface of the conductive post. The conductive post includes an intermetallic compound (IMC) layer in contact with the conductive bump. An upper surface of the IMC layer is lower than an upper surface of the encapsulation layer.

Abstract: A current sensor is described comprising an integrated circuit for sensing electric currents comprising an active side, the active side comprising at least one sensing element and at least one contact pad and a housing comprising material embedding the integrated circuit arranged for allowing electric connection to the at least two contact pads of the active side of the integrated circuit. The housing comprises at least one conductive via disposed outside the integrated circuit and connected to the at least one contact pad, for distributing signals from the at least one contact pad through the housing away from the active side of the integrated circuit.

Abstract: A light-emitting diode (LED) sub-chip and a method of producing the same are provided. The LED sub-chip comprises an epitaxial layer disposed on a growth substrate, where the epitaxial layer comprises a plurality of electrodes. The groove disposed between the LED sub-chip and a second LED sub-chip, where the groove penetrates through the epitaxial layer separating the two sub-chips. The bridge insulating layer at least partially covering a sidewall of the groove, where the sidewall comprises a first surface and a second surface above the first surface, where the texture of the second surface is less granular than a texture of the first surface. The bridge electrode on the bridge insulating layer, where the bridge electrode connects respective electrodes of the two sub-chips at the first surface.

Abstract: A semiconductor device is provided, including a seal portion; an electronic element within the seal portion; first, second, and third lead terminals; first and second connecting elements; and first and second conductive bonding agents, one end of the first connecting element having a protrusion downward and electrically connected to a control electrode of the electronic element with the first conductive bonding agent, a first side surface extending from the one end to the other end of the first connecting element is parallel to an extending direction along which the one end of the second connecting element extends, a wall portion being disposed on a top surface of the one end of the second lead terminal, and the wall portion being in contact with the other end of the first connecting element.

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate. The first source/drain region and the second source/drain region are separated by the channel. The example apparatus further includes a gate separated from the channel by a dielectric material and an access line formed in a high aspect ratio trench connected to the gate. The access line includes a first titanium nitride (TiN) material formed in the trench, a metal material formed over the first TiN material, and a second TiN material formed over the metal material. The example apparatus further includes a sense line coupled to the first source/drain region and a storage node coupled to the second source/drain region.