Abstract: In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both.

Abstract: A remote-controlled computer system includes a computer system electrically linked to a remote control device. The remote control device receives a manual operation to generate a manual trigger signal sent to the computer system. The computer system includes a motherboard, a power supply and a status control unit. The motherboard receives continuously the manual trigger signal and sends a power ON/OFF signal to start or stop the power supply. The power supply provides electric power to the motherboard for booting and a power activating signal to the motherboard. The status control unit is electrically connected to the motherboard, power supply and remote control device. The status control unit receives the manual trigger signal from the remote control device and transmits to the motherboard. The status control unit also detects absence of the power activating signal output from the power supply and stops sending the manual trigger signal.

Abstract: Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, a memory device stores data in response to data accesses under the control of a memory control circuit. A solid-state memory circuit and a volatile caching memory circuit provide the memory control circuit with access to a set of common data. A circuit carries primary operating power to the memory device. A backup power circuit has a power module having and securing a power-reservoir circuit. A capacitor holds a charge to provide operating power to the memory circuits to permit transfer of the data from the volatile memory circuit to the solid-state memory circuit. A notification circuit provides an external user indication of the power-reservoir circuit integrity. A circuit-based structure secures the power-reservoir circuit for operation as part of the memory device and facilitates replacement of the power-reservoir circuit.

Abstract: A power gating device may include a control unit that generates a first interrupt signal based on a mode change signal when a mode of a system is changed from a normal operation mode to a stand-by mode, and generates a second interrupt signal based on the mode change signal when the mode is changed from the stand-by mode to the normal operation mode, a memory unit that stores data of a function block based on the first interrupt signal, and restores the stored data to the function block based on the second interrupt signal, and a power source unit that provides a normal operation power to the function block and the memory unit based on a power down signal in the normal operation mode, and provides a stand-by power to the memory unit based on the power down signal in the stand-by mode.

Abstract: A method for starting up the communication device includes searching a non-volatile storage unit of the communication device for start up data of the communication device according to a predetermined identifier of the start up data, loading the start up data into a volatile storage unit of the communication device, starting the communication device according to the start up data in the volatile storage unit. The method also includes searching the non-volatile storage unit for data except for the start up data, load the data except for the start up data into the volatile storage unit.

Abstract: A mechanism for target host optimization in a load balancing host and virtual machine (VM) selection algorithm is disclosed. A method of embodiments of the invention includes determining that one or more collected metrics have triggered a load balancing operation of a host controller machine, identifying a plurality of source host machines and a plurality of virtual machines (VMs) hosted by the plurality of source host machines as candidates for selection by the load balancing operation for migration, and adjusting a selection score for at least one of a candidate source host machine and a candidate VM based on one or more metrics of the candidate source host and of the candidate VM, wherein the one or more metrics are associated with one or more candidate target host machines to which a candidate VM could be migrated.

Abstract: An AC-to-DC power adapter provides DC power to an information handling system at a first higher DC voltage or a second lower DC voltage based upon a power state of the information handling system. For example, approximately 19 Volts DC power is provided if the information handling system is in an on state or if the information handling system is charging a battery. Approximately 13 Volts DC power is provided if the information handling system is in a reduced power state, such as an ACPI S3 state, with a battery having a substantially full charge.

Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.

Abstract: In one embodiment, a peripheral controller coupled to a processor can include a storage controller. This storage controller can control access to a non-volatile storage coupled to the peripheral controller. The storage may include both secure and open partitions, and the storage controller can enable access to the secure partition only when the processor is in a secure mode. In turn, during unsecure operation such as third party code execution, visibility of the secure partition can be prevented. Other embodiments are described and claimed.

Abstract: A mechanism for shared memory history optimization in a host selection algorithm for VM placement is disclosed. A method of embodiments of the invention includes determining candidate hosts to place a target virtual machine (VM), obtaining memory sharing history of the target VM with one or more VMs hosted by each of the candidate hosts, determining an average memory sharing history amount for each of an optimized number of the candidate hosts based on the obtained memory sharing history of the target VM with one or more VMs hosted by each of the optimized number of candidate hosts, and adjusting a score in a general selection algorithm for a candidate host with the highest average memory sharing history amount.

Abstract: A method, system, and computer usable program product for improving processor performance during power supply failure are provided in the illustrative embodiments. A throttled condition of a processor is detected in a data processing system. A voltage of the electrical power being provided to the processor is reduced. The processor is un-throttled. Additionally, a frequency of electrical power being provided to the processor may also be reduced. A determination is made whether a condition that caused the throttling has been corrected. In response to the condition having been corrected, the frequency is returned to normal frequency and the voltage is returned to normal voltage. The reducing the frequency operation and reducing the voltage operation may each be performed by distinct components communicating over a data network external to the data processing system.

Abstract: An I/O device includes a host interface configured to process function level reset (FLR) requests in a specified amount of time. The host interface includes a control unit and groups of configuration space registers, each group corresponding to a function. The host interface also includes application availability registers, each associated with a respective function, and which may indicate whether application hardware within the respective function is available for access by a corresponding application device driver. The I/O device also includes application hardware resources associated with a respective function. In response to receiving an FLR request of a particular function, the control unit may cause the associated application availability register to indicate that the application hardware within the particular function is not available to the driver.

Abstract: Embodiments of the present invention include a method, apparatus, system, and/or computer program for monitoring energy consumption in a network and producing a display grid that provides a visual depiction of network device power consumption at any given time. The method includes, in one example, receiving a request for a power level schedule for a network device. The request may include a time period or date range over which the power level schedule should be produced. The method may also include retrieving Cron job strings associated with the network device, and parsing the Cron job strings to determine transitions from one power level to another and times for the transitions of the power level of the network device. The method further includes building a visual grid that depicts the power level schedule for the network device during each hour of the time period, based on the determined transitions.

Abstract: A power management system for home entertainment networks having three power states. The network controller is empowered to move nodes within the home entertainment network between the power states.

Abstract: Following a loss of power, a storage system switches to a local power supply. The system switches to the local power supply, prevents the receipt of input/output commands and copies the content of cache memory to a local storage device. On detecting resumption of external power, the system charges a local power supply, copies the content of the local storage device to the cache memory and processes the content of the cache memory with respect to at least one storage volume. When the charge stored on the local power supply exceeds the charge required to copy the content of the cache memory to the local storage device by a predetermined amount, the system allows the receipt of input/output commands using a reduced portion of the cache memory. Once the charge stored on the local power supply has reached a predetermined level, the system allows the receipt of input/output commands using all cache memory.

Abstract: Administering computer processor execution of BIOS code that includes a primary BIOS code and a recovery BIOS code stored in ROM, the ROM operatively coupled to a control module and the processor, where administering processor execution of the BIOS code includes determining, by the control module, a size of the ROM; generating, by the control module in dependence upon the size of the ROM, an address for the primary BIOS code and an address for the recovery BIOS code; starting, by the control module, operation of the processor for execution of the primary BIOS code including providing, to the processor, the address for the primary BIOS code; and if executing the primary BIOS code fails, restarting, by the control module, operation of the processor for execution of the recovery BIOS code including providing, to the processor, the address for the recovery BIOS code to the processor.

Abstract: Following a loss of power, a storage system switches to a local power supply. The system switches to the local power supply, prevents the receipt of input/output commands and copies the content of cache memory to a local storage device. On detecting resumption of external power, the system charges a local power supply, copies the content of the local storage device to the cache memory and processes the content of the cache memory with respect to at least one storage volume. When the charge stored on the local power supply exceeds the charge required to copy the content of the cache memory to the local storage device by a predetermined amount, the system allows the receipt of input/output commands using a reduced portion of the cache memory. Once the charge stored on the local power supply has reached a predetermined level, the system allows the receipt of input/output commands using all cache memory.

Abstract: A power supply system for supplying power to a number of loads includes a number of power supply modules, a bus, and a control module. The power supply modules each comprises an input terminal receiving an input power and an output terminal outputting an output power, the input terminals of power supply modules having the same input power. The bus is configured for connecting the loads to the power supply modules. The control module calculates the ratio of the total output power of the power supply modules to the input power of one power supply module and controls the connection and the disconnection of the power supply modules according to the ratio.

Abstract: In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both.

Abstract: A certain process included in a first execution space requests a local resource manager to allocate a resource. The local resource manager obtains the authentication ID of the process issuing the request and determines whether or not the resource can be allocated. If the resource can be allocated and the resource previously secured in the execution space can suffice the request, the local resource manager allocates the resource to the process. If the resource is insufficient, the local resource manager requests a global resource manager to allocate the resource. The global resource manager obtains the authentication ID of the first execution space issuing the request and determines whether or not the resource can be allocated. If it is determined that the resource can be allocated, the resource is allocated to the first execution space.