Abstract: A system and method for managing a power mode of a designated electronic device are provided. A geographical location of a mobile electronic device is determined. A comparison of the determined geographical location of the mobile electronic device and a stored location of a designated electronic device in a power-off mode is made. A wake-up signal is sent to the designated electronic device if the determined geographical location of the mobile electronic device is within a proximity threshold of the designated electronic device, where the designated electronic device is configured to enter a power-on mode upon receipt of the wake-up signal.

Abstract: The present invention relates to optimizing the performance of a data storage device, such as a hard data storage device, during boot operations and normal operations. In particular, during power up, the data storage device monitors the nature and progress of commands issued from a host. During boot operations, the data storage device sets its cache to a boot mode. The boot mode is designed to speed the boot process and aggressively cache data used during boot up of the data storage device and the host. The data storage device detects the transition of the host operations from boot operations to normal operations based on various criteria. The caching mode of the data storage device is then changed for normal operations based on the transition.

Abstract: A calling device may obtain a first calling security parameter by registering with a network and obtain a second calling security parameter in response to causing an application authentication architecture of the network to verify that that the calling device is authorized to access a network service corresponding to a communication application stored by the calling device. The calling device may communicate the first and second calling security parameters to a called device and receive first and second called security parameters from the called device in response to communicating the first and second calling security parameters. The calling device may generate a security key based on the first calling security parameter, the second calling security parameter, first called security parameter, and the second called security parameter, and use the security key to encrypt or decrypt communication between the calling device and the called device.

Abstract: A request handler may receive an image capture request for an operating system (OS) executing on a server. A pre-boot image handler may generate a pre-boot image, based on the image capture request and on the executing operating system. An image handler may capture an image of the operating system, based on the pre-boot image.

Abstract: In accordance with various aspects of the disclosure, a method and apparatus is disclosed that includes features of a host computing device, and a wireless power transmission module and a wireless data transmission module both integrated on a circuit board of the host computing device. The host computing device is configured to transmit power and multi-media data to a peripheral device, upon receipt thereof from the wireless power transmission module and the wireless data transmission module, respectively. The peripheral device is configured to receive wirelessly power and multi-media data from a host computing device, and provide the received power and multi-media data to a wireless power reception module and a wireless data reception module, respectively, for processing, both modules being integrated on a circuit board of the peripheral device.

Abstract: A technique provides apparatuses, methods, and computer readable media for sending sleep information from an end device to a central unit of a network, in which the wake-up time of the end device is aligned to the scanning time for the central unit. The technique addresses at least two considerations: the clock accuracy of the end device is accounted for, and the reason that the end device requests sleep mode operation is provided. To address the above considerations, the end device may send its clock tolerance information and/or request for sleep mode (RSM) command to the central unit once the end device is connected via the network. The central unit may then adjust the scanning time based on the clock tolerance information. If the central unit receives a response from the end device during the adjusted scanning time, the central unit deems that the end device is still connected.

Abstract: Embodiments of apparatus, computer-implemented methods, computing devices, systems, and computer-readable media (transitory and non-transitory) are described herein for scheduling a plurality of tasks among a plurality of processor cores. A first processor core of a plurality of processor cores of a computing device may be transitioned to a shielded state, in which no new tasks are to be assigned to the first processor core and tasks already assigned to the first processor core are executed to completion, in response to a determination that a criterion has been met. In various embodiments, the criterion may be based on a condition of the computing device, such as power available to the computing device or a temperature associated with the computing device. In various embodiments, the first processor core may transition to a reduced-power state after the tasks already assigned to the first processor core execute completion.

Abstract: A mechanism for firmware to gain control from the operating system of an Advanced Configuration and Power Interface (ACPI)-compliant computing device during sleep-state transitions even if the computing device lacks a dedicated means for such a change to occur is discussed. Embodiments of the present invention report a CPU-only reset register in place of a sleep control register for an ACPI-compliant computing device in which an operating system is attempting a sleep-state transition. A CPU reset value is substituted for a sleep type value in a sleep-state object and written to the CPU-only reset register that was reported instead of the sleep control register thereby triggering a CPU-only reset. Firmware code operating at a known CPU reset vector may perform specified processing and then authorize a transition to the originally requested sleep-state.

Abstract: A scheduler may receive a plurality of jobs for scheduling of execution thereof on a plurality of computing nodes. An evaluation module may provide a common interface for each of a plurality of scheduling algorithms. An algorithm selector may utilize the evaluation module in conjunction with benchmark data for a plurality of jobs of varying types to associate one of the plurality of scheduling algorithms with each job type. A job comparator may compare a current job for scheduling against the benchmark data to determine a current job type of the current job. The evaluation module may further schedule the current job for execution on the plurality of computing nodes, based on the current job type and the associated scheduling algorithm.

Abstract: A re-characterization process is provided that adjusts one or more operating parameters of a processor to improve the health (e.g., reduce errors) of the processor. The parameters include voltage and/or clock frequency, as examples. The processor can be an inactive or active processor for which the re-characterization process is performed. It is performed, in one instance, by a hardware controller in real-time.

Abstract: An approach to generating logical configuration commands for logical objects in a system. A method may involve receiving a command requesting the logical configuration commands to configure the specified logical object (subject logical object) and the logical objects that support the logical object (the support logical objects). The method may also involve determining what logical objects in the system support the subject logical object. This may require determining the support logical objects that directly support the subject logical object, and then recursively examining each support logical objects to find the logical objects on which they depend. For each logical object (whether the subject logical object or one of the support logical objects), the method may involve determining the logical configuration commands to appropriately create and modify the logical object. The logical configuration commands may then be presented to the user.

Abstract: A service provider can maintain one or more host computing devices that can be accessed as host computing device resources by customers. A hosting platform includes components arranged in a manner to limit modifications to software or firmware on hardware components. In some aspects, the hosting platform may include a master latch that indicates whether the components may be configured, and the master latch may be set once and only reset upon completion of a power cycle. In another aspect, the hosting platform can implement management functions for establishing control plane functions between the host computing device and the service provider that is independent of the customer. Additionally, the management functions can also be utilized to present different hardware or software attributes of the host computing device.

Abstract: A re-characterization process is provided that adjusts one or more operating parameters of a processor to improve the health (e.g., reduce errors) of the processor. The parameters include voltage and/or clock frequency, as examples. The processor can be an inactive or active processor for which the re-characterization process is performed. It is performed, in one instance, by a hardware controller in real-time.

Abstract: Power supply voltage to an integrated circuit (IC) or a portion of an IC is maintained at an optimum level matching the IC performance. Voltage ranges and delay measures for corresponding operating frequencies are stored in tables in a voltage control block. When a new frequency of operation is desired, the voltage control block measures delay performance of the IC, and sets the supply voltage to a value specified in a corresponding entry in a table. The voltage control block then continues to measure delay performance, and dynamically adjusts the power supply voltage to an optimum value thereby minimizing power consumption.

Abstract: USB physical interface subsystems are provided that include a protection circuit including a power supply interface and a plurality of pin interfaces, a pin identifier circuit in communication with the protection circuit for detecting a device coupling to a pin connected to one pin interface of the plurality of pin interfaces, a USB physical interface, and a dual power supply regulator configured to receive power via the power supply interface, to continuously supply a first voltage to the protection circuit, and to provide a second voltage and a third voltage to the pin identifier circuit and the USB physical interface, the second voltage and the third voltage being switched outputs.

Abstract: An information handling system server chassis manages plural server resources disposed on sleds in chassis slots with a power supply control board that allocates power from one or more power supplies to the slots. The power supply control board interfaces with an external network and includes one or more network interface cards that provide an Ethernet interface with power distribution boards disposed on sleds in the slots. The power distribution boards manage application of power to server resources and communication by the power supply control board through the Ethernet interface to manage functions at the server resources.

Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

Abstract: A system, computer-implemented method, and computer program product for undeployment of a business process definition in a cluster-enabled business process management runtime environment are presented. A BPMS server executes, through a deployment container executing one or more business processes instances of a business process definition running across a cluster of nodes, a stop operation of a running process instance of the business process application. The BPMS server further executes a remove operation of the stopped running process instance from the deployment container.

Abstract: An image processing apparatus includes: a switch of a main power supply unit that is switched between ON and OFF in response to a user's operation so as to switch the power supply between a supply of power and an interruption of the supply; a first notification unit that sends an interrupt request notification for requesting to interrupt a process in a recoverable way to all of or a part of the applications being run if the switch of a main power supply unit is turned off; and a power supply control unit that interrupts the supply from the power supply when a time lapse, that is measured since a time when the notification unit has sent the interrupt request notification, exceeds a first predetermined time.

Abstract: Systems and methods are disclosed which relate to improving synchronization of clocks between a sender and a receiver communicating via an asynchronous serial interface. In a ring topology, a master device is connected to a plurality of slaves communicating using a bi-frequency encoded bit stream. A host device communicates with the master device using a non-return-to-zero data encoding. Each slave receives data from the master and sends it to the next slave in the ring unaltered unless the master indicates a requirement for a particular data, and transmits placeholder bits with a value of 0 around the ring. A particular slave can “fill-in” the placeholder bits with the information to be sent back to the master by inverting the placeholder bit. Clock synchronization between a receiving device and a transmitting device is improved using a fractional rate multiplier to generate a data sampling clock from a system clock.