Abstract: Systems and methods may provide for securely transferring data from a flash component. In one example, the method may include receiving a download request from an embedded controller chip, obtaining information from the flash component in response to the download request, and transferring the information to the embedded controller chip.

Abstract: A power grid stabilizing system may include a processor and a network interface executable by the processor to monitor for new event data from power consumption devices over a network. The new event data may include information such as device location, operating information, and sensor data. The system may include an estimation engine operable to analyze the new event data to determine power consumption behavior of a consumption device, and a predictor operable to anticipate an occurrence of a future event responsive to the analysis. The predictor may also predict the outcome of the future event based on analysis of the new event data in relation to past behavior data of the consumption device. The network interface may further communicate the anticipated future event and the predicted outcome to one or more of the other consumption devices.

Abstract: A configurable mission processor (CMP) is disclosed that includes a chassis with a plurality of reprogrammable processor modules (RPMs) disposed within the chassis. Each RPM has a baseboard with at least one field programmable gate array (FPGA) and a configuration manager configured to accept a configuration file through an externally accessible signal connector, store the configuration file, and selectably program the at least one FPGA using the configuration file. The RPM includes a power submodule that accepts unregulated power through an externally accessible power connector, generates regulated power at a plurality of voltages, and provide the regulated power to the RPM. The RPM may also include an input/output submodule configured to provide a communication channel between the at least one FPGA and external devices through its own externally accessible signal connector. The CMP also includes a backplane that provides only signal and ground interconnections between the baseboards.

Abstract: Aspects of the present disclosure are directed to providing power from two or more power sources. As may be implemented in accordance with one or more embodiments, a switching circuit includes a switching transistor connected between a backup power supply and both a primary power supply and an internal power rail. When power is provided via the primary power supply, the switching circuit operates in a blocking state in which back current is prevented from flowing to the backup power supply while the primary power supply couples power to the internal power rail. When the primary power supply is disconnected or interrupted, a voltage coupled to a gate/control terminal of the switching circuit drops and the switching circuit automatically switches to another state in which the internal power rail is powered by the backup power supply.

Abstract: An AC-to-DC power adapter provides DC power to an information handling system at a first higher DC voltage or a second lower DC voltage based upon a power state of the information handling system. For example, approximately 19 Volts DC power is provided if the information handling system is in an on state or if the information handling system is charging a battery. Approximately 13 Volts DC power is provided if the information handling system is in a reduced power state, such as an ACPI S3 state, with a battery having a substantially full charge.

Abstract: A computing device, such as a mobile communication device, is provided that adjusts, based on user interaction with the device, sleep times for a display to enter a sleep mode restricting use of a graphical user interface. The device includes a display providing the graphical user interface and a processor. The processor is configured to cause the display to enter the sleep mode after a sleep time without receiving any user inputs, increase the sleep time responsive to a user input received within a predetermined period of time after entry of the sleep mode and decrease the sleep time responsive to another user input directing the display to enter the sleep mode before passage of the sleep time. The processor may execute similar processes to adjust a plurality of sleep times associated with different applications and different functions within an application.

Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.

Abstract: In an example, in a method for providing a shutdown process for a computer system including an operating system (OS), basic input/output system (BIOS) firmware may capture a request from the OS to hardware of the computer system to enter into a hibernate state. In addition, the BIOS firmware may determine whether a hybrid-shutdown process is in process and in response to a determination that the hybrid-shutdown process is in process, may turn off the computer system instead of entering the computer system into the hibernate state.

Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.

Abstract: Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.

Abstract: A hearing assistance system including a hearing instrument designated as a master device and at least another hearing instrument designated as a slave device. The master device is communicatively coupled to the slave device via a wireless link. The master device has a master clock and generates master time stamps for specified events timed by the master clock. The master time stamps are sent to the slave device via the wireless link. The slave device has a slave clock and generates slave time stamps for specified events timed by the slave clock. The slave clock is adjusted for synchronization to the master clock using the master time stamps and the slave time stamps.

Abstract: Systems and methods for controlling power usage of devices in information handling systems are provided. A device for use in an information handling system may include a connector and an auxiliary power connector. The connector may be configured to electrically couple to a device connector such that the device transmits and receives data via the device connector and receives electrical current from a power supply via the device connector. The auxiliary power connector may be configured to electrically couple the device to the power supply such that the device receives electrical current from the power supply via the device connector, the auxiliary power connector including at least one sense line, the at least one sense line configured to receive at least one power control signal. The device may be configured to establish its power usage in response to receiving the at least one power control signal.

Abstract: Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.

Abstract: An electronic apparatus is provided that includes a processor, a voltage regulator, a battery controller and an embedded controller. The voltage regulator to receive an input voltage and to provide an output voltage to the processor. The battery controller to store electronic device information and to receive battery information related to a current battery power. The embedded controller to receive the electronic device information and the battery information from the battery controller, and the embedded controller to provide power information to the processor based on the received information.

Abstract: A service provider can maintain one or more host computing devices that can be accessed as host computing device resources by customers. A hosting platform includes components arranged in a manner to limit modifications to software or firmware on hardware components. In some aspects, the hosting platform may include a master latch that indicates whether the components may be configured, and the master latch may be set once and only reset upon completion of a power cycle. In another aspect, the hosting platform can implement management functions for establishing control plane functions between the host computing device and the service provider that is independent of the customer. Additionally, the management functions can also be utilized to present different hardware or software attributes of the host computing device.

Abstract: The subject matter of this specification can be embodied in, among other things, a method that includes supplying power to a portion of a data center through a power distribution line. Utilization of a statistically significant sample of the computers is monitored, and an estimated individual power draw for each of the computers based on the utilization is calculated. An estimated total power draw is calculated for different times from the estimated individual power draws to generate a collection of estimated total power draw values for the different times. Actual power draw is monitored at the power distribution line and a collection of actual power draw values is generated. A function is fitted to pairs of actual power draw values and estimated power draw values, each pair comprising an actual draw value and an estimated draw value for the same time, and the function is then stored.

Abstract: A power excursion tolerant power system includes at least one powered component. A system capacitance and at least one power supply are coupled to the at least one powered component. The at least one power supply is operable as a voltage controlled current source to supply power to the at least one powered component when a system load is below a predetermined threshold. The at least one power supply is operable as a constant current source, and together with the system capacitance, to supply power to the at least one powered component when the system load is above the predetermined threshold. A load reduction mechanism is coupled to the at least one powered component and operable to perform at least one load reduction action when the system load is above the predetermined threshold.

Abstract: Systems and methods for facilitating on-demand delivery and processing of one or more programs and program-compatible applications on a plurality of different machines. In an embodiment, a metadata-driven command processor on a machine sends a request for a booting program and application to an agent. In response to the request, the agent invokes a resource to generate a booting program dataset that defines the booting program and an application dataset that defines the application, generates a response dataset comprising two or more nested datasets, wherein the two or more nested datasets comprise at least the booting program dataset and the application dataset, and sends the response dataset to the metadata-driven command processor. The metadata-driven command processor copies the booting program dataset and the application dataset into a process dataset comprising two or more nested datasets, and processes the first process dataset to execute the booting program and application on the machine.

Abstract: A method includes initiating a boot of a system-on-chip coupled to a boot device. The boot is initiated from boot code stored in nonvolatile memory responsive to a power-on-reset. Under control of the boot code: a first register value is loaded into a register; a name string from the boot code is accessed; the first register value is obtained from the register; and the first register value and name string are converted to a first string value, which is provided as a first filename. The boot device is searched for a boot image file with the first filename. If the first filename is not found in the boot device, the first register value is incremented to provide a second register value. The obtaining, converting, and searching are repeated using a second filename generated using the second register value, and a valid filename for the boot image file is iteratively generated.

Abstract: A card with power management circuitry is provided. A card may have circuitry contained therein (e.g., a processor) that may have a maximum operating voltage. The card may include a power source (e.g., a battery) that provides power ranging in voltage from a maximum power source voltage to a minimum power source voltage. The maximum power source voltage is greater than the maximum operating voltage. Power management circuitry is provided to manage the power received from the power source such that the voltage provided to the circuitry (e.g., processor) does not exceed the maximum operating voltage.