Abstract: An electronic device may include a printed circuit with a surface-mounted component. The component may produce resistive heating within the printed circuit. Resistive thermal devices (RTDs) may be embedded within the printed circuit. An RTD may at least partially overlap the electrical component. The RTD may include contact pads on a flexible substrate and a meandering conductive trace between the contact pads. The trace may have a resistance varying linearly as a function of temperature. A data acquisition system (DAQ) may measure the resistance of the RTD. Control circuitry may identify the temperature of the printed circuit based on the resistance of the RTD measured by the DAQ and may reduce power consumption by the component when the temperature exceeds a threshold. This may serve to prevent overheating in the printed circuit over time, thereby maximizing the operating life of the printed circuit.

Abstract: An information processing device includes an acquisition unit that acquires a power load indicating time-series data of power of an energy storage device in a first period, a classification unit that classifies each power load obtained by dividing a power load acquired by the acquisition unit for each second period shorter than the first period into a plurality of groups, and an extraction unit that extracts, for each group classified by the classification unit, a representative power load from among power loads for each second period belonging to each group.

Abstract: A server power supplying method and system, a device, and a medium are provided by the present application, the method includes: connecting a first device in a server system based on a first power supply, and connecting a second device in the server system based on a second power supply, wherein the first power supply and the second power supply are electric power supplies of the server system; after the server system is powered on, acquiring power supply information of the server system and determining the power supply information; in response to the power supply information being first power supply information, configuring a power supply enable signal of the first power supply to enable the first power supply to supply power to the first device in the server system.

Abstract: A power supply device includes a charge-discharge switching element connected in series to a battery module and configured to charge and discharge the battery module, an analog circuit configured to control turning on and off of the charge-discharge switching element, and a digital circuit configured to control the analog circuit. The analog circuit includes an analog-side communication terminal configured to receive, from the digital circuit by communication, an instruction controlling turning on and off of the charge-discharge switching element, and a switch-OFF terminal configured to turn off the charge-discharge switching element. The switch-OFF terminal is different from the analog-side communication terminal. The power supply device further includes a switch-OFF circuit configured to output an OFF signal to turn off the charge-discharge switching element to the switch-OFF terminal in response to a non-operating state of the digital circuit.

Abstract: Systems and methods of the present disclosure provide techniques for reducing power consumption of a large combinational circuit using register insertion. In particular, a large circuit may be analyzed to determine the amount of signal switching at various logical points (e.g., stages in the computation) of the circuit. A clock sequence with many pulses in the period of a clock that runs the large combinatorial circuit may be generated. To balance the amount of signal switching at various logical points in the circuit, registers may be inserted at certain points in the large circuit with the clock pulses of the clock sequence assigned to the registers that may not have a constant frequency or may be phase shifted versions of the main clock.

Abstract: Power control in a computing device may include timing a periodic time interval associated with intervals of memory accesses by a first processor alternating with intervals of inactivity of the first processor, and powering down memory controller circuitry during the intervals of first processor inactivity while maintaining power supplied to a system-level cache. Maintaining the power supplied to the system-level cache may allow a second processor to continue accessing the system-level cache even while the memory controller circuitry is powered down. Power may be restored to the memory controller circuitry during the intervals of memory access by the first processor.

Abstract: An electronic device stores a target program representation containing information of a program for an electronic part of the electronic device. A controller obtains a certificate issued by a certificate authority, the certificate including a program version enforcement information element to indicate whether program version enforcement is to be applied using the target program representation. The controller checks the program version enforcement information element in the certificate to determine whether the program version enforcement is to be applied, and based on determining from the certificate that the program version enforcement is to be applied, the controller enforces application of a version of the program indicated by the target program representation to the electronic part.

Abstract: A foldable electronic device includes a first power management module, a first load, and a first battery pack disposed in a first foldable portion of the foldable electronic device. A second power management module, a second load, and a second battery pack are disposed in a second foldable portion in the foldable electronic device. The first power management module controls the first battery pack to supply power to the first load, and the second power management module controls the second battery pack to supply power to the second load. The foldable electronic device further includes an isolation circuit, and the isolation circuit may perform voltage balancing on voltages of two connected batteries.

Abstract: The present techniques relate to mitigating droop conditions over state transitions in systems having dynamic voltage and frequency scaling and there is disclosed a method of controlling a dynamic voltage and frequency scaling circuit, comprising: initiating a transition from a first voltage and frequency state to a second voltage and frequency state; switching activity from a first nominal source to a first fallback source; retuning the first nominal source to become a second fallback source at the second voltage and frequency state; switching activity from the first fallback source to the second fallback source; retuning the first fallback source to become a second nominal source at the second voltage and frequency state; and switching activity from the second fallback source to the second nominal source.

Abstract: The present specification discloses an arithmetic processing device which has a high processing rate with a low cost. The arithmetic processing device according to the present specification is an arithmetic processing device comprising a fetch unit which reads data required for a calculation for performing processing of a neural network from a memory, and provides the data to an arithmetic unit. The fetch unit may include: a fetch buffer into which data stored in each of data memory slices is fetched; and an interface controller for assigning a node ID corresponding to each of the data memory slices to the data fetched into the fetch buffer, and controlling a timing of outputting the fetched data according to the node ID.

Abstract: A computing system includes a central processing unit (CPU), a baseboard management controller (BMC) coupled to the CPU via a first communication protocol, and a boot non-volatile memory. The BMC includes a first communication protocol controller, a BMC memory, a root of trust, and an internal BMC bus. The internal BMC bus is configured to communicatively couple the BMC memory, the first communication protocol controller, and the root of trust. The boot non-volatile memory is coupled to the BMC via the first communication protocol controller. The boot non-volatile memory is configured to store basic input/output system (BIOS) firmware and/or BMC firmware.

Abstract: The present disclosure provides methods, electronic apparatuses and storage media for voltage regulation. An example method includes acquiring a current working state of the memory system, and reducing a voltage provided to the memory system in response to the current working state being a light-load working state.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to monitor and manage usage of resources on a computing platform. An example apparatus includes a processor and a subsystem. The example processor includes a modified operating system, the operating system modified to monitor application execution via the processor to determine a usage scenario for the apparatus. The example processor includes an index generator to generate a system usage scenario index quantifying a snapshot of the usage scenario for the processor and the subsystem of the apparatus. The example processor includes a rebalancer to reallocate resources of at least one of the processor or the subsystem based on the system usage scenario index.

Abstract: Methods and systems involving automotive computing architectures with phased wake sequences and power control are disclosed herein. A disclosed automotive computing system includes at least three subsystems: a first subsystem that is in an always-on power domain, a second subsystem that is powered on from a sleep state in response to an event detected by the first subsystem, and a third subsystem that is powered on, from an off state, after the first subsystem and the second subsystem are powered on. The subsystems of the architecture can be activated in different phases based on a given scenario in which the automotive computing architecture is operating. The same subsystem can occupy a different phase in different scenarios. The phased wake sequences may conserve power without sacrificing utility and may be optimized for different scenarios and triggering events.

Abstract: A system and method for securing a system-on-chip (SoC) field programmable gate array (FPGA) is provided, wherein the SoC FPGA includes an FPGA fabric, a soft core processor hosted within the FPGA fabric, a hard core processor, and a secure boot environment for the SOC FPGA. Monitoring logic monitors for a change in the FPGA fabric. External watchdog logic is configured to receive a trigger signal from the monitoring logic, and force the hard core processor(s) of the SoC FPGA into a reset state with no ability to recover unless power is cycled when a change has been made to the FPGA fabric, so as to provide a “fail secure” scenario. The monitoring logic may be firmware hosted on the FPGA fabric, software hosted on the soft core, software hosted on the hard core, and/or external hard logic.

Abstract: The information processing apparatus and method are designed to: extract features about requirements including at least a data structure of data to be handled by the target system to be created, a method for analyzing the data, and a method for searching the data; extracts catalogs which satisfy the features of the extracted requirements from among a plurality of kinds of catalogs which are prepared in advance and define data processing flows; extract respective cloud services suited for the requested requirements with respect to each service constitute element of the extracted catalogs; generate one or a plurality of proposed system configurations obtained by combining the extracted cloud services in accordance with the extracted catalogs; and present each of the generated proposed system configurations.

Abstract: Some embodiments are directed to a computer-implemented method to convert a first computation network of operations into a second computation network of operations. The operations of the second computation network being fully homomorphic encrypted (FHE) operations. The converting may include obtaining for the input values of the operation a supported range of the input value in the first computation network, and determining a prescribed range for the input values of a corresponding FHE operation.

Abstract: Systems and methods for integrating generative artificial intelligence (AI) capabilities within Software as a Service (SaaS) platforms. One of the computer-implemented methods are for querying a generative AI model about structured data in a SaaS environment, enabling users to interact with and manipulate data through AI-assisted interfaces. One of the systems maintains a generative AI agent configured to interact with SaaS platform data as a virtual team member, capable of understanding context and nuances of project data. Also described are methods for color-context aware data analysis, generation of interactive elements in messaging sessions, and cross-application generative AI agent interactions triggered by user mentions. Also described is facilitating the creation of custom SaaS platform products by combining functionalities from existing products using generative AI. The systems and methods represent advancement in AI-driven SaaS customization and data analysis.

Abstract: An electronic device is provided. The electronic device includes a housing, a flexible display including a sliding plate and a bendable section, a multi-bar structure supporting the bendable section, a sensor circuit configured to detect a first state in which at least a part of the bendable section enters an internal space of the housing or a second state in which at least a part of the bendable section is drawn out from the housing, at least one temperature sensor, and a processor. The processor obtains a temperature of one or more heating elements through the at least one temperature sensor in the first state, identifies at least one heating element having a temperature higher than a designated temperature, and controls the at least one heating element having the temperature higher than the designated temperature to operate according to a first execution policy.

Abstract: Apparatuses, systems, and techniques to allocate power to one or more processors. In at least one embodiment, processors or computing systems perform an API to allocate power to one or more processors based, at least in part, on indications of priority of one or more threads to be performed by the one or more processors.