Abstract: A computing node is configure to implement an intra-node network boot and installation protocol (protocol) for booting and installing an operating system (OS) on a virtual machine hosted on the computing node without communicating over a physical network. The protocol includes hosting a dynamic host configuration protocol (DHCP) server instance and/or a network boot server instance on a controller virtual machine of the computing node to emulate DHCP protocol and network boot server protocol communications. In some examples, the protocol further utilizes one or more virtual extensible local area networks (LANs)(VXLANs) and a virtual switch hosted at a hypervisor running on the computing node.

Abstract: An information handling system may include a host system comprising a host system processor, a logic device configured to perform a functionality of the information handling system in accordance with code stored on non-transitory computer-readable media of the logic device, and a management controller communicatively coupled to the host system processor and the logic device and configured to perform out-of-band management of the information handling system. The management controller may be further configured to: during a boot of the management controller, perform an initial authentication of the code via an immutable interface of the logic device, after the initial authentication and prior to completion of boot of the management controller, enable a hardware lock to prevent write access to the logic device via the immutable interface, and in response to a power on request of the host system, perform a second authentication of the code via a mutable interface of the logic device.

Abstract: The present disclosure provides novel and improved information processing apparatus, information processing method, and program with which it is easy for a user to predict a future remaining battery amount. According to the present disclosure, there is provided an information processing apparatus including a control unit that performs control to calculate a future prediction value of remaining battery amount on the basis of a use history of an information processing apparatus by a user and to present prediction value related information related to the prediction value to the user. According to the present disclosure, the user can easily predict the future remaining battery amount. Note that the effects described above are not necessarily limitative. With or in the place of the above effects, there may be achieved any one of the effects described in this specification or other effects that may be grasped from this specification.

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to provide device enhancements for software defined silicon implementations are disclosed. Example apparatus disclosed herein include a request interface to receive a request for a timestamp. Disclosed example apparatus also include a property checker to determine a first value of an electrical property of a feature embedded in a silicon product, the feature having electrical properties that change over time. Disclosed example apparatus further include a relative time determiner to calculate a relative time between the request and a previous event based on the first value of the electrical property and a second value of the electrical property, the second value of the electrical property associated with the previous event.

Abstract: The present invention discloses an asymmetrical PN junction thermoelectric couple structure and its parameter determination method. By changing the structural parameters of p-type semiconductor or n-type semiconductor, the current generated by p-type semiconductor is equal to the current generated by the n-type semiconductor, so that the high-efficiency output of PN junction thermoelectric couple can be realized. Meanwhile, the present invention provides a method for determining the parameters of PN junction based on the numerical solution method. Finally, the optimal size parameters of PN junction are obtained.

Abstract: Techniques regarding resetting highly excited qubits are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a reset component that can de-excite a qubit system to a target state by transitioning a population of a first excited state of the qubit system to a ground state and by applying a signal to the qubit system that transitions a population of a second excited state to the first excited state.

Abstract: The driver Hamiltonian is modified in such a way that the quantum approximate optimization algorithm (QAOA) running on a circuit-model quantum computing facility (e.g., actual quantum computing device or simulator), may better solve combinatorial optimization problems than with the baseline/default choice of driver Hamiltonian. For example, the driver Hamiltonian may be chosen so that the overall Hamiltonian is non-stoquastic.

Abstract: Systems, computer-implemented methods, and computer program products that can facilitate a classical and quantum ensemble artificial intelligence model are described. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an ensemble component that generates an ensemble artificial intelligence model comprising a classical artificial intelligence model and a quantum artificial intelligence model. The computer executable components can further comprise a score component that computes probability scores of a dataset based on the ensemble artificial intelligence model.

Abstract: Examples provided herein provide a manner of monitoring performance characteristics of a central processing unit or other instruction executing hardware device and adjusting settings of the central processing unit or other instruction executing hardware device. Performance characteristics can be gathered and stored in a secure memory or storage device. The performance characteristics can be transmitted to a control center using a provisioned network transceiver that does not rely on an operating system executed by the central processing unit or the hardware platform of the central processing unit. The control center can determine settings that are to be applied by the central processing unit or instruction executing hardware device and transmit the settings for use by the central processing unit or instruction executing hardware device.

Abstract: Systems and methods that address an optimized method in the area of optimization by showing how to generate Ising Hamiltonians automatically for a large class of optimization problems specially handling the constraints. The innovation facilitates qubit reduction in connection with an optimization problem by representing respective integer variables as linear sums of binary variables, wherein depending on the representation, additional equality constraints are provided. Additional slack variables are introduced to change inequality constraints to equality constraints. Based on the equality constraints, an unconstrained pseudo-boolean optimization problem is created. The pseudo-boolean optimization problem is quadratized to generate a quadratic pseudo-boolean function (QPBF) and the number of variables in the QPBF is reduced to facilitate qubit reduction. This results in an automated, problem instance dependent qubit reduction procedure.

Abstract: In a general aspect, input data for a computer process are preprocessed by a preprocessor unit that includes a quantum processor. In some aspects, a preprocessor unit obtains input data for a computer process that is configured to run on a computer processing unit. Randomized parameter values are computed for variable parameters of a quantum logic circuit based on the input data. A classical processor in the preprocessor unit computes the randomized parameter values from the input data and a set of random numbers. A quantum processor in the preprocessor unit produces quantum processor output data by executing the quantum logic circuit having the randomized parameter values assigned to the variable parameters. Preprocessed data generated based on the quantum processor output data are then provided as the input for the computer process configured to run on the computer processing unit.

Abstract: A sealed enclosure power control system for controlling power to an electrical component within an enclosure. The sealed enclosure power control system generally includes an electrical component within the sealed enclosure, a first connector on the sealed enclosure adapted to provide a sealed electrical interface to the electrical component. The first connector has at least one first connector conductor element, and the system further includes a battery within the sealed enclosure, and the system also has a second connector, wherein when the first connector and the second connector are connected together, electrical power from the battery is applied to the electrical component, and when the first connector and the second connector are not connected together, the electrical power is not applied to the electrical component.

Abstract: A circuit breaker comprises a solid-state bidirectional switch, a switch control circuit, current and voltage sensors, and a processor. The solid-state bidirectional switch is connected between a line input terminal and a load output terminal of the circuit breaker, and configured to be placed in a switched-on state and a switched-off state. The switch control circuit control operation of the bidirectional switch. The current sensor is configured to sense a magnitude of current flowing in an electrical path between the line input and load output terminals and generate a current sense signal. The voltage sensor is configured to sense a magnitude of voltage on the electrical path and generate a voltage sense signal. The processor is configured to process the current and voltage sense signals to determine operational status information of the circuit breaker, a fault event, and power usage information of a load connected to the load output terminal.

Abstract: Systems and methods for power distribution by an ethernet controller are disclosed. A first input port receives a first power carried by a first ethernet cable and sourced by a first source PoE device. A second input port receives a second power carried by a second ethernet cable and sourced by a second source PoE device. The first input port is at a first voltage lower than a minimum voltage of a specified input voltage range and the second input port is at a second voltage lower than the minimum voltage of the specified input voltage range. A controller, coupled to the first and second input ports, substantially equalizes current flowing across a first output port and a second output port, coupled to the downstream PoE devices, such that a load, caused by the downstream PoE devices, between the first output port and the second output port is shared.

Abstract: In a method of checking normal input power and load of a programmable AC power distributor in its power-on state, indicator lights are installed in an output ON button and an output OFF button. During power ON, a master switch is switched to an ON position to detect the input power and obtain a detection result through a change of the indicator light in the output OFF button, and then the output ON button is pressed to check the power-on state of the load and obtain a detection result by outputting the change of the indicator light of the button. Therefore, users can instantly know whether the input power and load are in a normal state during the operation of turning on the power distributor, and this method makes the operation of the power distributor safer and more convenient, and ensures a high quality of power supply.

Abstract: Disclosed in various embodiments are an electronic device, the electronic device comprising: a power control circuit for controlling power supplied to at least one component of the electronic device; at least one submergence recognition circuit including a first pole connected to at least one port of the power control circuit, and a second pole connected to a ground; a processor electrically connected to the power control circuit; and a memory electrically connected to the processor, wherein the memory can be configured, during execution thereof, to store instructions for allowing the processor to: control the power control circuit such that power is supplied to the submergence recognition circuit; sense a current flowing from the submergence recognition circuit to the power control circuit; and determine, on the basis of the sensing result of the current, whether an area in which the submergence recognition circuit is arranged has been submerged.

Abstract: A power and data communication system including an inboard computer system that includes a resistor network, an outboard computer system that includes at least one current limiter and voltage limiter that receives power from the inboard computer in order to power electronics of the outboard computer, and first and second wires connecting the resistor network of the at least one current limiter.

Abstract: A compiler for a gate-based superconducting quantum computer compiles hybrid classical/quantum algorithms for quantum processing cells with different configurations. The compiler inputs the algorithm and outputs code in a target language executable by a quantum processing cell of a quantum processing system that can execute the algorithm. The compiler includes various functionality, such as: parsing, analyzing control flows, addressing, compressing, and translating. The compiler optimizes algorithms in various manners using the functionality. Some optimizations include addressing efficiently, compressing based on simulations, and translating for efficient execution of parametric functions. The compiler may function in the environment of a cloud quantum computing system. The cloud quantum computing system may receive algorithms from remote access nodes for execution on local classical and quantum computing systems.

Abstract: A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

Abstract: A total power requirement for a plurality of memory operations is estimated. It is determined that the total power requirement would meet a power budget. In in response to determining that the total power requirement would meet the power budget, a power profile identifier associated with a first operation of the plurality of memory operations is adjusted. The first operation and the power profile identifier are issued to a memory device. The power profile identifier is used by the memory device to regulate an amount of power used when performing the first operation.