Patents Examined by Terrell S Johnson
  • Patent number: 10488902
    Abstract: A device and method for controlling a voltage applied to processor cores of a processor are disclosed. The method includes processing a plurality of tasks on the processor with a plurality of processor cores and applying a rail voltage to the plurality of processor cores. The number of the plurality of processor cores that are active is adjusted, and the rail voltage that is applied to the plurality of processor cores is adjusted based upon the number of the plurality of processor cores that are active.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: November 26, 2019
    Assignee: QUALCOMM Innovation Center, Inc.
    Inventors: Sajjad Pagarkar, Karthik Ranganathan Vishwanathan
  • Patent number: 10474214
    Abstract: An apparatus and method for monitoring the power storage capability of a secondary power source of a data storage device is provided. A capacitor is used as a secondary power source. A charging path and a discharging path are selectively generated for the capacitor. After being charged through the charging path, the capacitor is then discharged through the discharging path while the charging path is disconnected from the capacitor. Then, the capacitor is checked to determine whether its voltage level has dropped below a threshold level and thereby an evaluation result obtained from evaluating the capacitor is generated.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: November 12, 2019
    Assignee: SHANNON SYSTEMS LTD.
    Inventor: Xiawei Ye
  • Patent number: 10466737
    Abstract: A control system for overclocking a computer is disclosed. The control system includes a casing for housing a computer assembly and, on the casing, a control device electrically connected to the computer assembly, a display device electrically connected to the control device, an operation device data-linked to the control device, and a fan device electrically connected to the control device so as to be controlled by the operation device.
    Type: Grant
    Filed: August 6, 2017
    Date of Patent: November 5, 2019
    Assignee: EVGA CORPORATION
    Inventor: Yu-Sheng Han
  • Patent number: 10459742
    Abstract: An information handling system includes a memory and a central processor. The memory stores a firmware update for a component of the information handling system. The central processor is operable in a pre-boot mode and in an operating system runtime mode. The central processor, while in the operating system runtime, updates a location of the firmware update in the memory via a unified extensible firmware interface (UEFI) runtime service, and triggers a firmware update for the component, via the UEFI runtime service, by a boot option number being set to a BootNext EFI variable.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: October 29, 2019
    Assignee: Dell Products, LP
    Inventors: Wei Liu, Po-Yu (Smith) Cheng
  • Patent number: 10460362
    Abstract: Aspects of performing power management operations in a distributed computer system are described. In some aspects, predicted demand data is generated for clients executed in a cluster of host computers. The predicted demand data is based on observed resource demands of the clients. A power management setting for a time period is determined. The power management setting is based on the predicted demand data. A host computer is caused to power-down or power-up in order to apply the power management setting.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: October 29, 2019
    Assignee: VMWARE, INC.
    Inventor: Aashish Parikh
  • Patent number: 10459505
    Abstract: A method of controlling a computing device including a physical battery and at least one group of applications executable on hardware resources of the computing device, each group including one or more applications. The method comprises controlling each group of applications based on a state of a respective virtual battery associated each group of applications, each virtual battery having a respective virtual capacity corresponding to a defined portion of a capacity of the physical battery and a respective virtual battery reserve representing an amount of energy that is available for use by the group of applications associated with the virtual battery.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: October 29, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Michael Mayer, Mehdi Arashmid Akhavain Mohammadi
  • Patent number: 10430197
    Abstract: According to one general aspect, an apparatus may include a register circuit and an instruction scheduler circuit. The register circuit may include a plurality of physical registers that are partitioned into at least a common portion that is associated with a predefined plurality of instructions, and a shared portion, and a plurality of write ports, wherein each portion is associated with at least one respective write port. The instruction scheduler circuit configured to determine an instruction, and rename an architectural register associated with the instruction to a physical register. Wherein the portion including the physical register is selected based, at least in part, upon a characteristic of the current instruction.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ankit Ghiya
  • Patent number: 10429912
    Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Krishnakanth Sistla, Martin Rowland, Efraim Rotem, Brian J. Griffith, Ankush Varma, Anupama Suryanarayanan
  • Patent number: 10423430
    Abstract: Embodiments are disclosed for methods and systems for selectively initializing elements of an operating system of a computing device. In some embodiments, a method of selectively loading classes during an initialization of an operating system of a computing device comprises starting a service-loading process, loading critical services via the service-loading process, and launching a human-machine interface. The method may further include launching a last-used application via the human-machine interface, and launching remaining services responsive to requests for use of the remaining services.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: September 24, 2019
    Assignee: Harman International Industries, Incorporated
    Inventors: Prakash Raman, Pranjal Chakraborty, Eugine Varghese
  • Patent number: 10416738
    Abstract: A method for adjusting a pull resistor on a contact terminal of an electronic module arranged on a printed circuit board, in particular an ASIC, after initiating a restart of the electronic module which, during a run-up process, moves the electronic module from a switched-off state into a switched-on state, wherein after initiating a restart during the run-up process from a partial circuit arranged on the electronic module and operationally ready during the run-up process, adjustment information relating to a desired adjustment of the pull resistor is retrieved from a storage unit arranged on the printed circuit board outside of the electronic module and transmitted via a contact line between the electronic module and the storage unit, where the run-up process of the electronic module is only completed after successful adjustment of the respective pull resistor based on basis the retrieved adjustment information.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: September 17, 2019
    Assignee: Siemens Aktiengesellschaft
    Inventors: Friedrich Eppensteiner, Majid Ghameshlu, Martin Matschnig, Herbert Taucher
  • Patent number: 10409318
    Abstract: An information processing device includes: a receiver that compares a serial input signal to a threshold value and outputs reception data; an extraction circuit that extracts a clock superimposed on the reception data from the reception data; a measurement circuit that measures a pulse width of the reception data based on the clock; a counter that measures an elongation and a shortening of the pulse width; and an adjustment circuit that increases the threshold value when the elongation of the pulse width is larger than a reference value, and reduces the threshold value when the shortening of the pulse width is larger than the reference value.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: September 10, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Hiroshi Sakurai
  • Patent number: 10394573
    Abstract: A method of a storage area network (SAN) includes storing and communicating data received from a server at a host bus adapter via a bus controller of the adapter. In a case where the data is associated with an address corresponding to a default boot logical unit (LUN) of a non-volatile memory (NVM) of the adapter, the data is stored in the NVM. In a case where the data is not associated with an address corresponding to a boot LUN of the NVM, the data is communicated over the SAN. During power up of the adapter, in a case where it is determined that the NVM includes an image of an operating system, the adapter uses the bus controller to provide the server with information to select the NVM as a boot LUN for booting the operating system.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: August 27, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventor: Ketan Mukadam
  • Patent number: 10387337
    Abstract: An apparatus includes a communication interface, a controller, and a power section. The communication interface is configured to receive power from an external host to the apparatus. The controller is configured to limit a current drawn by the communication interface to a predetermined value when the apparatus is powered through the external host. The power section is configured to generate a first voltage from a portion of the limited current drawn by the communication interface. The first voltage powers a data storage circuitry. The power section is further configured to store electrical charges received from another portion of the limited current drawn by the communication interface. The power section is further configured to generate a second voltage from the stored electrical charges in response to a signal from the controller. The second voltage supplements the first voltage during high power events by the data storage circuitry.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: August 20, 2019
    Assignee: Seagate Technology LLC
    Inventors: John Wayne Shaw, Robert John Dore, Christopher A. Massarotti, Philip Jurey, Ashutosh Razdan, Philip Yin, Michael Gene Morgan
  • Patent number: 10387165
    Abstract: In an approach for selecting a boot-up path in a multi-node server, a processor receives a first set of computing capability data for a first boot-up path of a server and a second set of computing capability data for a second boot-up path of the server. A processor compares the first set of computing capability data to the second set of computing capability data. A processor determines that the first boot-up path has greater computing capabilities than the second boot-up path based on the comparison. Responsive to determining the first boot-up path has greater computing capabilities, a processor boots-up the server using the first boot-up path.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Raja Das, Venkatesh Sainath, Vishwanatha Subbanna, Dhruvaraj Subhashchandran Pillai
  • Patent number: 10386907
    Abstract: A computing device is associated with a circuit for sharing and distributing backup power. During normal operating conditions, a main bus bar provides power to each computing device in a rack via a main power bus of the corresponding circuit. In the event of an AC power outage, the main power bus is deactivated and a backup power path of the circuit is activated. Backup power is provided to the device from a battery of the circuit via the backup power path. A shared power path is also activated in the circuit such that backup power may be provided from the battery to the main bus bar. By providing backup power to the main bus bar, the other computing devices in the rack that do not have sufficient backup power may receive backup power from the main bus bar until AC power is restored.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 20, 2019
    Assignee: Google LLC
    Inventors: Udaya Kiran Ammu, Tracy Jane Van Dyk, Cornelius O'Sullivan, Srikanth Lakshmikanthan
  • Patent number: 10389336
    Abstract: One embodiment describes a Josephson transmission line (JTL) system. The system includes a plurality of JTL stages that are arranged in series. The system also includes a clock transformer comprising a primary inductor configured to propagate an AC clock signal and a secondary inductor arranged in a series loop with at least two of the plurality of JTL stages. The clock transformer can be configured to propagate a single flux quantum (SFQ) pulse to set a respective one of the plurality of JTL stages in response to a first phase of the AC clock signal and to reset the respective one of the plurality of JTL stages in response to a second phase of the AC clock signal that is opposite the first phase.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: August 20, 2019
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Donald L. Miller, Ofer Naaman
  • Patent number: 10379596
    Abstract: In one embodiment, a processor includes: a plurality of cores; a power controller including a logic to autonomously demote a first request for at least one core of the plurality of cores to enter a first low power state, to cause the at least one core to enter a second low power state, the first low power state a deeper low power state than the second low power state; and an interface to receive an input from a system software, the input including at least one demotion control parameter, where the logic is to autonomously demote the first request based at least in part on the at least one demotion control parameter. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Nir Rosenzweig, Efraim Rotem, Yoav Ben-Raphael, Alon Naveh
  • Patent number: 10379589
    Abstract: An example disclosed herein is a non-volatile storage medium including instructions relating to control of power that, when executed by a processor, cause the processor to monitor a supply of power to a regulator, decouple supply of power to the regulator when the monitored supply of power is below a predetermined level, couple a power pack to the regulator to supply power to the regulator when the monitored supply of power is below the predetermined level, and generate an Advanced Configuration and Power Interface (ACPI) G1 Sleeping state signal when the monitored supply of power is below the predetermined level.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: August 13, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Patrick Ferguson, Chien-Hao Lu, Chih Liang Li, Szu Tao Tong
  • Patent number: 10372188
    Abstract: A method includes a power supply system receiving a first request for a first quantity of power for a first time period from a first unit. The system generates a first quote based on an available power generation capacity, environmental factors and a forecasted level of power consumption. The system transmits the first quote to the first unit. The system receives a second request for a second quantity of power for a second time period. The system generates a second quote based on the same factors as the first quote. The system transmits the second quote to the second unit. The value of the first quote and the value of the second quote are set to discourage demand in a first mode and to encourage demand in a second mode to maximize efficient operating levels of the power generation sources in both the first mode and the second mode.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: August 6, 2019
    Inventor: Robert F. Cruickshank, III
  • Patent number: 10360041
    Abstract: A method is disclosed. The method may include detecting whether a first electronic device is in an inserted state in a second electronic device. The method may include switching the first electronic device to an “on” state in response to detecting that the first electronic device is in the inserted state in the second electronic device. In particular, the first electronic device may function as a master device and the second device may function as a slave device in response to the first electronic device switching to the “on” state. An electronic device and a program product are also disclosed.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: July 23, 2019
    Assignee: Lenovo (Beijing) Limited
    Inventors: Chong Zhu, Fenglong He