Abstract: An integrated RS flip-flop circuit comprises two cross-coupled inverters which respectively consist of a field effect transistor and a resistor connected in series. Each field effect transistor is connected to an additional logic element whose control input represents the R or the S input, respectively. Realization of a flip-flop circuit on the smallest possible semiconductor is achieved by designing the additional logic elements as hot electron transistors, each of which is combined with one of the field effect transistors to form a common component which assumes two transistor functions but only requires the area of one field effect transistor. The invention is particularly useful in VLSI circuits.

Abstract: A semiconductor junction related structure to control sensitivity of signal processing systems to signals of greater versus smaller values.

Abstract: An MOS integrated circuit has an array of terminal means connectable to an output buffer or the like arranged around an array of MOS circuit components such as shift registers or the like and has a novel metal programmable matrix arranged for compactly and economically accommodating any selected interconnection of the shift registers and terminal pins at the metal conductor level of the integrated circuit.

Abstract: A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 .mu.m, as well as a method for fabricating the choice, is disclosed. The inventive device, which is formed in a substrate comprising a relatively heavily doped bulk region supporting a relatively thin, moderately doped layer, includes a polysilicon-filled trench extending through a portion of the layer, between the n- and p-channel FETs of the device. The inventive device also includes a relatively heavily doped region extending from a bottom of the trench to the bulk region. The polysilicon-filled trench, in combination with both the relatively heavily doped region and bulk region, prevents latchup.

Abstract: A semiconductor memory device, such as a MOS dynamic RAM device, having memory cells each comprising a transfer gate transistor and a capacitor. The capacitor is a so-called groove-type capacitor and has a conductive layer formed on an insulation film attached to the inside surface of a groove formed on a semiconductor substrate. The conductive layer is electrically coupled to the source of the transfer gate transistor. The capacitance of the capacitor is formed between the conductive layer and a second conductive layer formed on the conductive layer via an insulation film, and/or between the conductive layer and the semiconductor substrate.

Abstract: A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 .mu.m, as well as a method for fabricating the device, is disclosed.The inventive CMOS device includes a latchup-preventing, polysilicon-filled trench formed in the semiconductor substrate between the n- and p-channel FETs of the device. The polysilicon-filled trench is essentially free of crack-inducing voids, and achieves a width less than 10 .mu.m, because the angle between the trench sidewall and a perpendicular drawn to the substrate surface is greater than, or equal to, about 5 degrees but less than about 10 degrees. Also, a thickness of the polysilicon deposited into the trench is greater than half the width of the trench.

Abstract: An integrated circuit has small signal MOS logic transistors formed in an N-type basket which basket itself is formed in an N-type epitaxial pocket that is defined by an enclosing P-type isolation wall. In a second epitaxial pocket a relatively high-current carrying bipolar transistor is formed. The MOS containing N-type basket is tied to one DC voltage which the substrate and isolation walls are connected to a lower level DC voltage. Substrate currents that are caused by the high current in the bipolar transistor are prevented by the N-type basket from inducing voltage changes in the MOS transistors.

Abstract: An insulated gate electrostatic induction transistor and an integrated circuit employing such an insulating gate electrostatic induction transistor as a drive transistor. A highly resistive channel region is provided on a semiconductor substrate of higher conductivity. A highly doped source region is formed adjacent the channel region, and a gate electrode, separated from the channel region by a thin insulating layer, is formed above the channel region. The gate electrode has a high diffusion potential with respect to the source region. The depth of the highly doped source region is less than that of a distribution of carriers in an inversion layer formed under the gate electrode.

Abstract: An IGFET device includes a semiconductor wafer having a first conductivity type drain region contiguous with a wafer surface. A second conductivity type body region extends into the wafer from the wafer surface so as to form a body/drain PN junction having an intercept at the surface; the body region further including a body-contact portion of relatively high conductivity disposed at the surface. A first conductivity type source region extends into the wafer so as to form a source/body PN junction which has first and second intercepts at the surface. The first intercept is spaced from the body/drain intercept so as to define a channel region in the body region at the surface, and the second intercept is contiguous with the body contact portion. The second intercept is relatively narrowly spaced from the first intercept along most of the length of the first intercept and is relatively widely spaced from the first intercept at one or more predetermined portions.

Abstract: An electrical device which employs two-dimensional space charge modulation in a semiconductor structure. The device has an approximately Debye length wide contact and a rectifying contact positioned adjacent to each other within a Debye length on a semiconductor body and a contact remotely positioned. A bias on the rectifying contact will effect conduction between the other contacts.

Abstract: A power FET is preceded by an input amplifier consisting of a second FET of the same channel type and a third FET of an opposite channel type. The FETs of the pre-amplifier can be integrated into the chip of the power FET without additional production steps if the power FET and the second FET are designed as vertical FETs and the third FET as a lateral FET. Through this semiconductor device, the relatively high input capacitance of power MISFETs, which results in slow switching speeds when driven by standard ICs, is overcome.

Abstract: A zener diode structure for integrated circuits is disclosed. The device includes a pair of parallel zener diodes connected back to back with a third zener diode. The anode of one of the parallel diodes is connected to the anodes of the other two diodes through a parasitic resistance. The zener breakdown junctions of two of the diodes are well below the surface of the device thereby reducing any adverse affect of stray surface charges and ultraviolet radiation. Further, the doping levels of the opposing diodes are selected to reduce drift in the breakdown voltage due to variations in operating temperature of the device.

Abstract: An integrated circuit power supply interconnection technique is disclosed having a highly doped, low resistivity substrate for distribution of the integrated circuit's most positive supply voltage. The substrate functions as the most positive voltage point and accomodates devices that are normally connected directly to this most positive supply voltage. A dielectric buried layer overlies a portion of the substrate and isolates the substrate supply voltage from devices that are not connected directly to the most positive supply voltage.

Abstract: A capacitor is disclosed having two capacitor elements of MIS structure, the capacitor elements being connected in a zigzag manner to realize a balanced parallel connection for the capacitor elements. A circuit having a pair of balanced impedance branches, the branches being bridged by the balanced parallel capacitor disclosed above, resultantly sustains the impedance branches balanced regardless of the amount of the parasitic capacity involved.

Abstract: Disclosed is an overvoltage protection structure which when used with CMOS circuits it protects them from overvoltage conditions while minimizing latch-up conditions in the structure. It consists of a well region of an opposite conductivity to that of the substrate defining a pocket region having a conductivity type which is similar to that of the substrate. A first PN junction diode is formed in a portion of the well region and a second PN junction diode is formed in the pocket region. The two diodes have opposite polarity and they both are connected to a signal line in such a way that one of the two diodes will be forward biased if the voltage on the signal line exceeds the bounds of the power supply voltages. The pocket region is connected to a V.sub.SS terminal which is normally grounded and the well region is connected to a power supply V.sub.DD.

Abstract: The invention relates to a power transistor with a semiconductor body. When shutting off a power transistor, local fusing of the semiconductor body may occur, if a characteristic power loss is exceeded for a certain period of time (second breakdown). This can be avoided, if the transistor includes a multiplicity of small partial transistors with very narrow emitter zones which are mutually paralleled via a ballast resistance each.

Abstract: A static storage cell is formed of two cross-coupled inverters each containing a field effect transistor and a resistor element connected in series therewith. Each circuit node is thus connected via an additional logic element to a bit line allocated thereto. A storage cell is provided which is on as small as possible a semiconductor area and has a short access time. This is achieved by designing the additional logic elements as hot electron transistors which are respectively combined with one of the field effect transistors to form a common component which only requires the area of a field effect transistor. The cell is useful in VLSI semiconductor memories.

Abstract: A Darlington transistor circuit having a power transistor and a driver transistor is proposed. The two transistors are monolithically integrated in a common substrate (10) by a planar process, the substrate forming the collector zones of the two transistors. On the main surface of the substrate (10) there is a passivation layer (13) covering this main surface with the exception of contact windows. The base-collector junctions of the two transistors are protected by a metal electrode (15), which is located above the passivation layer (13) and extends up to a stop ring (14), which is disposed beneath the passivation layer (13) in the substrate (10). The potential at the cover electrode (15) is adjustable with the aid of a voltage divider (16). (FIG. 3).

Abstract: High voltage integrated circuit field plates that are connected directly to the epitaxial pockets over which they lie, are formed simultaneously with high resistivity polysilicon resistors and are insulated from cross-over metal by a dual insulation of silicon dioxide and silicon nitride. Without adding to these process steps, MNS capacitors are formed that have a higher packing density than their MOS counterparts. The space saving MNS capacitors are thus space-wise and process-wise compatible with the polysilicon field plates that occupy much less chip real estate than do diffused channel stops.

Abstract: This invention provides a structure for preventing input part and/or an output part of the semiconductor chip forming complementary MOS field effect transistors from being damaged by accumulated static charges, wherein regions of the conductivity types as and higher impurity concentrations than a semiconductor substrate and a well region, respectively, are formed at the respective surfaces to come in contact with each other such that diodes be formed and the diodes are connected to an electrode pad.