Patents Examined by Terri M. Henn
  • Patent number: 4549199
    Abstract: A semiconductor device comprises a connection structure composed of a first conductive layer formed in or on a semiconductor substrate, a second conductive layer arranged adjacent to the first conductive layer, and a third conductive layer connecting the first conductive layer to the second conductive layer. The device of the present invention provides a contact structure which can be miniaturized.
    Type: Grant
    Filed: July 14, 1983
    Date of Patent: October 22, 1985
    Assignee: Fujitsu Limited
    Inventors: Takahiko Yamauchi, Teruo Seki, Keizo Aoyama
  • Patent number: 4544938
    Abstract: A heterojunction photodiode with improved wavelength-selectivity and risetime. The problem of short-wavelength diffusion-tail response is avoided by interposing between the window and active layers a barrier layer of higher bandgap than that of the window layer, which prevents high-energy photocarriers generated in the window layer from diffusing to the PN junction. In one embodiment, n-type substrate, active, barrier, and window layers are initially grown, and the window layer is coated with an opaque oxide. A window is opened in the oxide layer, and a p-type dopant is diffused heavily through the opening, through the window layer, and partly into the barrier layer. A PN junction is thus formed in the barrier layer, its depletion region extending through the remaining n-type region of the barrier layer and into the active layer, where photocarriers are generated by photons passing through the window-opening.
    Type: Grant
    Filed: November 18, 1982
    Date of Patent: October 1, 1985
    Assignee: Codenoll Technology Corporation
    Inventor: Frederick Scholl
  • Patent number: 4538169
    Abstract: An apparatus is provided for sinking heat from the diodes of an alternator bridge whereby the heat is transferred directly to the alternator casting. A mounting base is mounted on the alternator case in a manner to provide both thermal and electrical conductivity. A thin layer of thermally conductive, but electrically isolating, epoxy is sandwiched between a plate and a portion of the mounting base. "Negative" diodes are placed on the mounting base and "positive" diodes are placed on the plate so that electrical contact is made. Heat from the "negative" diodes is transferred through the mounting base and from the "positive" diodes through the plate and mounting base to the alternator casting, thereby reducing the thermal resistance and eliminating a need for large, "finned" heatsinks. The "negative" diodes or "positive" diodes may comprise a low voltage avalanche die, thereby providing for high energy transient suppression in the alternator.
    Type: Grant
    Filed: November 4, 1982
    Date of Patent: August 27, 1985
    Assignee: Motorola, Inc.
    Inventors: William R. Smith, Theodore R. Myers
  • Patent number: 4532534
    Abstract: A vertical MOSFET device includes a major surface having an active, gate-controlled portion adjacent to an inactive portion. A gate-controlled perimeter channel is disposed at the boundary between the active and inactive portions.
    Type: Grant
    Filed: September 7, 1982
    Date of Patent: July 30, 1985
    Assignee: RCA Corporation
    Inventors: Raymond T. Ford, Norbert W. Brackelmanns, Carl F. Wheatley, Jr., John M. S. Neilson
  • Patent number: 4529999
    Abstract: An improved semiconductor device, particularly a gate controlled switch is provided by optimally fitting an involute spiral cathode-gate structure into a substantially square device. 4N cathode-gate branches radiate from a central gate portion and intersect the perimeter of the square device region at predetermined locations, N per side, where N is an integer. Four of the branches tangentially intercept the square perimeter at a distance R from a centerline where R is the radius of the central gate portion. The origin of the branches is angularly displaced from the line connecting the die center to the tangential intercept point by (L/R)- arctan (L/R) radians where L is half the edge length of the square device region. Improved thermal performance is obtained by thermally coupling the cathode heat spreader to the gate as well as cathode portions of the device.
    Type: Grant
    Filed: July 9, 1982
    Date of Patent: July 16, 1985
    Assignee: Motorola, Inc.
    Inventors: John R. Bender, James R. Washburn
  • Patent number: 4524376
    Abstract: A semiconductor device, for example a p-i-n diode, comprises a corrugated semiconductor body having a plurality of complementary grooves and ridges on opposite sides of the body. The junction between the p-type region and the n-type intrinsic region has substantially the same configuration as, and extends substantially parallel to, the surface, while the junction between the n-type region and the intrinsic region similarly extends substantially parallel to the surface. Devices with narrow intrinsic regions can be made accurately by diffusion of the p-type region and the n-type region because the whole of the diode can be made relatively thin, for example, 90 micrometers without sacrificing strength and rigidity. In comparison with an equivalent planar device, the active area and current handling capability is increased. To avoid premature breakdown the diode may be surrounded by a thicker peripheral portion.
    Type: Grant
    Filed: May 14, 1984
    Date of Patent: June 18, 1985
    Assignee: U.S. Philips Corporation
    Inventor: John A. Cornick
  • Patent number: 4523217
    Abstract: N-stage bipolar transistors are provided in a semiconductor substrate by using a manufacturing process of a CMOS LSI used for driving a solar powered electronic appliance. A reference voltage from a solar cell is applied to a base of a first bipolar transistor, and bases of i-th (i.ltoreq.n) bipolar transistors are connected to emitters of (i-1)-th bipolar transistors, thereby providing a constant voltage circuit in the semiconductor substrate.
    Type: Grant
    Filed: May 17, 1983
    Date of Patent: June 11, 1985
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Mitsuo Jibu
  • Patent number: 4516144
    Abstract: A Hall effect semiconductor device is provided with means for clipping or focusing emitted carriers to form a centralized columnated beam, and trimming means for accurately controlling the amount of magnetic deflection due to Lorentz force. Emitters from an emitter region travel through a base region under influence of an externally applied drift field toward a pair of spaced collector regions. The polarity of a perpendicularly applied magnetic field determines deflection of the carriers toward one or the other of the collector regions. The columnating means comprises a pair of spaced auxiliary collector regions intermediate the emitter region and the primary collector regions for collecting carriers not within a central angle or cone. A columnated beam is provided by carriers passing between the auxiliary collectors within the central angle or cone.
    Type: Grant
    Filed: September 23, 1982
    Date of Patent: May 7, 1985
    Assignee: Eaton Corporation
    Inventors: Stanley V. Jaskolski, Herman P. Schutten, Gordon B. Spellman, Jan K. Sedivy, Maurice W. Jensen
  • Patent number: 4513310
    Abstract: A first wiring to be connected as needed and second wirings to be disconnected as needed are formed three-dimensionally with an insulation film interposed therebetween. The first wiring comprises at least three first semiconductor regions of a second conductivity type formed at predetermined intervals in the surface of a semiconductor substrate of a first conductivity type, and second semiconductor regions of the first conductivity type formed between each pair of adjacent first semiconductor regions. The second wirings are formed on the first wiring through the insulation film and in a number equal to that of the second semiconductor regions. Each second wiring and the corresponding second semiconductor region are located within a spot of a radiating means radiated vertically onto the semiconductor substrate for switching the wirings.
    Type: Grant
    Filed: May 10, 1983
    Date of Patent: April 23, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Junichi Ohno, Satoshi Konishi
  • Patent number: 4499481
    Abstract: An FET with an extremely short channel formed by the apex of a substrate ridge structure protruding upward through the channel layer toward a Schottky-barrier gate contact. The device is formed by etching a modulation-doped substrate to form an upwardly protruding ridge with the apex modulation-doped. A semiconductor layer is then disposed over the substrate surface with the protruding ridge to obtain an epitaxial interface therebetween. Source and drain regions are doped into the semiconductor layer on opposite sides of the ridge structure. Finally, ohmic contacts are formed on the semiconductor layer over the source and drain regions and a Schottky-barrier metalization is deposited on the semiconductor layer above the ridge structure. This device has a very short channel, a low transit time, a low gate capacitance, and an enhanced transconductance.
    Type: Grant
    Filed: September 14, 1983
    Date of Patent: February 12, 1985
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Richard F. Greene
  • Patent number: 4481523
    Abstract: An avalanche photodiode sensitive to a wavelength range of from 1.2 to 1.65 micrometers is provided with a light absorbing layer, a middle layer and an active layer grown in order, on a substrate. All the layers contain impurities with the same conductivity but the impurity concentration is higher in the middle layer than in either of the light absorbing layer and the active layer. A p-n junction having a flat bottom and either a gradually inclined side or a step-shaped side is produced in the active layer, so that the breakdown voltage is made much less in the area facing the flat bottom of the p-n junction than in the area facing a side which has the aforementioned irregular shape. As a result, the side acts as a guard ring without being accompanied by a large amount of tunnel current flowing through the light absorbing layer in response to the intensity of the electric field.
    Type: Grant
    Filed: November 30, 1981
    Date of Patent: November 6, 1984
    Assignee: Fujitsu Limited
    Inventors: Fukunobu Osaka, Tatsunori Shirai