Abstract: A semiconductor device structure incorporates a semiconductor wafer having first and second opposing major surfaces and an edge. A first region of first conductivity type is contiguous with the second surface and includes an edge portion which is contiguous with the wafer edge at the first surface. A second region, of second conductivity type, extends into the wafer from the first surface so as to form a PN junction with the first region at a predetermined depth from the first surface. A third region, of second conductivity type, extends into the wafer from the first surface to a depth greater than the predetermined depth. The third region is disposed between and is contiguous with the second region and the edge portion of the first region. When the wafer is silicon the third region has an areal charge concentration of approximately 1 to 2.times.10.sup.12 cm.sup.-2.

Abstract: In a darlington transistor having an integrated resistor connected from base to emitter of the output transistor element, the effect of the diode between collector and emitter formed when the resistor consists of an extension to the base region is reduced by forming at least part of the resistor either as an extension to the emitter region or as a separate region of the same conductivity type and connected to it. The resistor formed by the emitter region material appears in series with the diode.

Abstract: A semiconductor device comprises a complementary FET circuit wherein respective gate and drain of a P-channel FET are commonly connected to those of an N-channel FET with each other, the common node of each gate serves as an input terminal, while the common node of each drain serves as an output terminal, and the source of each FET is connected to said first and second reference power sources. The semiconductor device further comprises an additional complementary FET circuit wherein respective gate and drain of a P-channel FET are commonly connected to those of an N-channel FET with each other, the common node of each drain is connected to the input terminal, while the common node of each gate is connected to the output terminal, and the source of each FET is connected to the output terminal, and the source of each FET is connected to the wafer of the complementary FET circuit.

Abstract: A back-to-back diode includes a substrate having five superimposed layers of hydrogenated amorphous silicon thereon. The first and fifth layers are of one conductivity type, the second and fourth layers are intrinsic, and the third layer is of the opposite conductivity type. The layers are all of the substantially the same thickness. A conductive layer contact is provided between the substrate and the first layer and a conductive layer contact is provided on the fifth layer. The intrinsic layers may include carbon alloyed with the hydrogenated amorphous silicon.

Abstract: Disclosed is a dumbbell-shaped resistor structure fabricated in a semiconductor substrate for determining the resistivity of the intrinsic base of a polysilicon base transistor. The structure includes an n-doped base region having two large parts separated by a narrow part, resembling a flattened dumbbell, each of which extends into the substrate. A p-type emitter region extends a distance into a portion of the narrow and the second large parts of the base region. An n-type reach-through region extends from the emitter region through the base region electrically isolating a portion of the narrow and second large parts of the base region from the remainder of the base region and forming an electrically continuous p-type path between the first large part of the base region and the portion of the second large part within the reach-through region.

Abstract: An FET logic gate structure includes two semiconductor layers separated by an insulator. An enhancement mode switching FET is formed in the top semiconductor layer, and a load element is formed in the bottom semiconductor layer. The insulator layer separates and capacitively couples the switching element and the load element so that the switching element acts as a gate for the load element and the load element acts as a second gate of the switching element. An input is connected to the gate of the switching element. The drain of the switching element, the source of the load element, and the output of the folded logic gate are connected together. The logic gate structure exhibits very low power consumption in stable states, high speed and large output voltage swings.

Abstract: A heterostructure bipolar transistor has an emitter layer, a base layer and a collector layer, the emitter layer being formed of a semiconductor material whose energy gap is wider than that of the base layer, so that a heterojunction is formed between the emitter layer and the base layer. One of the emitter layer and the base layer has first and second layers which are sequentially formed, and the first layer constituting the heterojunction has a lower impurity concentration than that of the second layer. When the impurity concentration and the thickness of the first layer are defined as N.sub.1 and W.sub.1, respectively, the following relation is satisfied:N.sub.1 W.sub.1.sup.2 .ltoreq.(2.epsilon..sub.s .epsilon..sub.0 /q)V.sub.biwhereq: the absolute value of electron charge(=1.6.times.10.sup.-19 Coulombs),.epsilon..sub.0 : the free space permittivity(=8.86.times.10.sup.-14 farads/cm),.epsilon..sub.s1 : the dielectric constant of the first layer, andV.sub.bi : the built-in potential at the heterojunction.

Abstract: A semiconductor device comprises a gate array portion formed in the central portion of a chip, and a number of CMOS input/output cells arranged at the peripheral portion of the chip. Each input/output cell consists of a bonding pad, a p-channel MOS region and an n-channel MOS region, and extends inward from the side of the chip in a direction perpendicular to the side of the chip.

Abstract: A circuit arrangement for FETs connected in parallel. In the arrangement the same electrode of N FETs (N>1) is connected by associated metallic conductors to a central conductor. A further metallic conductor is also connected to the central conductor. The shape of the central conductor is such that the FETs are mechanically equidistant from the connection of the further conductor. This equalizes the fall times between the FETs without the need to add any physical inductors to the circuit.

Abstract: This invention relates to an improved heterojunction FET. More specifically the invention is directed to a heterojunction FET device in which the contact to the semiconductor gate is ohmic in character. The gate and channel regions of the FET have the same barrier height relative to an intervening third layer of semiconductor and sandwich the third layer of undoped semiconductor. The resulting symmetry of the structure provides a threshold voltage which lies normally near zero volts and is controllable upwardly or downwardly by adding an n or p type dopant to the undoped third layer or region.

Abstract: An insulated-gate field-effect transistor which may be of a vertical power D-MOS type includes surface-adjacent source and emitter regions surrounded in a semiconductor body by a surface-adjacent second region of opposite conductivity type. A third region adjoins the second region and has a lower conductivity-type determining doping concentration. At least a part of these second and third regions is located in a main current path from the source region to a drain of the transistor, and an insulated gate, which may be of metal-silicide, capacitively controls a conductive channel at least in this part of the second region. The emitter region is located at a side of the source region remote from the channel part and is separated therefrom by an intermediate part of the second region. The source region is electrically connected to this intermediate part, for example by a short-circuiting metal-silicide layer.

Abstract: This invention relates generally to cryogenic amplifying-switching devices and more specifically relates to a cryogenic transistor with a superconducting base and a collector isolated from the base by a semiconductor element. Still more specifically, the invention is directed to a three terminal, transistor-like device which incorporates three metal layers. The first and second of the three layers are separated by an insulating tunnel barrier and the second and third layers are separated by a semiconductor layer of a thickness sufficient to inhibit tunnelling. The semiconductor layer has a barrier height (low) which is sufficient to permit the passage of quasiparticles from the second layer while simultaneously inhibiting the passage of Cooper pairs. The second layer is a superconductor while the first and third layers may be superconductors or normal metals. The second and third layers are connected to the semiconductor layer by means of ohmic contacts.

Abstract: A radial type of high voltage solid-state switch is essentially a gated diode switch (GDS) with portions of the anode, cathode, shield, and gate regions being arc portions of concentric circles which have different radii. The arc length and radius of the arc portions of the anode are less than the corresponding parameters of the shield and cathode. This structure, which is denoted as a radial gated diode switch, RGDS, has lower on resistance than a standard GDS of the same area and distance between anode and shield regions.

Abstract: Inversion-mode insulated field-effect transistor structures are provided wherein a lightly-doped GaAs drift or drain region is combined with a gate-controlled channel structure comprising a film or layer of a semiconductor layer other than GaAs and within which inversion regions may more readily be formed. Suitable semiconductor materials for the gate-controlled channel structure are InP and Ga.sub.x In.sub.1-x As. Presently preferred is a Ga.sub.x In.sub.1-x As graded layer wherein x ranges from 1.0 to about 0.47.

Abstract: A semiconductor fuse is disclosed that provides protection against both overcurrent and the abrupt application of a voltage to semiconductor devices. A first means is coupled to an input terminal for providing a signal when a current is applied to the input terminal. A second means is coupled between the input terminal and an output terminal for allowing current to pass therebetween and is coupled to the detecting means and responsive to the signal. A third means is coupled between the output terminal and a ground terminal for shorting a current therebetween. A fourth means is coupled to the input terminal, the second means, and the third means for activating the third means and preventing the second means from responding to the signal when the input current exceeds a predetermined value.

Abstract: The present invention relates to cross-sectional shape of a silicon gate electrode of an insulated gate field effect transistor. The gate electrode is composed of polycrystalline silicon, and its length, in cross section, gradually increases from the surface contacting to the gate insulating film toward the central portion thereof and then gradually decreases toward the upper surface thereof. The central portion of the polycrystalline silicon has the largest length in the source-drain direction and contains small amount of SiO.sub.2 particles. Relying upon this gate shape, the portion having largest length, can be used as a mask to introduce impurities in a self-aligned manner to form source and drain regions. The thus formed source and drain regions create small capacity relative to the gate electrode. Therefore, a high speed transistor is realized.

Abstract: A multicolor or other multilevel infrared detector comprises at least one first detector element formed in a first portion of a lower body, e.g. of cadmium mercury telluride. At least one second detector element, having different detector characteristics, is formed in an upper body, e.g. of cadmium mercury telluride. The lower body is divided, preferably by ion etching into at least two (and more usually three or more) portions separated from each other by gaps. The gaps in the lower body are bridged by the upper body. Electrical connections to the second detector elements comprises the separate portions of the lower body. The electrical connections include metallization layers extending from the top to the substrate on which the lower body is mounted. The substrate may be of insulating material, e.g. sapphire, or it may be for example a silicon CCD for processing signals from the detector elements.

Abstract: A semiconductor device for controlling a current comprises a pn junction formed of a high resistivity region and a relatively low resistivity region, a graded distribution of dislocation density is formed in the high resistivity region and decreases with an increase in distance from the pn junction, also graded distribution of lifetime killer concentration is formed in the high resistivity region and decreases with an increase in distance from the pn junction in correspondence with the graded distribution of dislocation density.

Abstract: In order to provide low and exactly repeatable common lead inductance (gate lead inductance) and low feedback parasitics in a common-gate low noise amplifier, a GaAs FET connects the gate electrode to ground at various points along its width by means of an air bridge crossover structure. This structure crosses over the input (source) lines with very low capacitance. Since the gate lead inductance is low in this design, and because in monolithic form this inductance does not vary as is the case for a device grounded using bond wires, common-gate circuit stability is assured. This device preferably uses the well-known pi-gate configuration to provide low drain-gate parasitic capacitance and equal phasing to all parts of the device.

Abstract: A lateral bipolar transistor is described incorporating at least two grooves extending from the upper surface and spaced apart by a predetermined amount from which impurities are introduced to form an emitter region extending from the sidewall of one groove and a collector region extending from the sidewall of an adjacent groove with the base being the substrate material between the two regions. A plurality of grooves may be utilized to form a plurality of transistors with the grooves staggered to facilitate access to the ends of the grooves functioning as emitters and those functioning as collectors. The large vertical junction area formed by the side walls relative to the horizontal junction area at the bottom of the grooves and the uniform base width result in a high current gain lateral transistor.