Abstract: Embodiments of the present invention bias a field effect transistor with only a single voltage source and generally do not have the disadvantages of traditional "floated source" bias techniques. Furthermore, some embodiments of the present invention are capable of automatically compensating for the normal manufacturing variations that occur in the physical characteristics of individual FETs.

Abstract: A power conserving integrated circuit is disclosed. The integrated circuit is coupled to its external power supply only in response to an external event. An initial power connection is made in response to the external event. An element on the integrated circuit detects the initial power connection. After detecting the initial power connection, a switch internal to the integrated circuit is closed so as to couple the power supply to the integrated circuit for a predetermined period of time sufficient for a function to be executed by the integrated circuit. Afterwards, the connection is terminated and is not re-initiated until another external event. Therefore, power is consumed only when necessary, thereby preserving the power source.

Abstract: This invention deals with the problem of an error voltage in a MOSFET analog switch sample and hold circuit caused by the turn off charge in the MOSFET analog switch. The invention provides a compensating circuit which can be adjusted to exactly compensate for the turn off charge which causes the error so that the error can be reduced to zero or nearly zero. The compensating circuit can be used in both open loop and closed loop sample and hold circuits. The compensating circuit can be used in combination with a Miller feedback circuit for eliminating the error voltage.

Abstract: A biasing circuit (30) for an output vertical pnp transistor (10) formed in an integrated circuit and having an outer epitaxial region (20) includes a biasing vertical pnp transistor (33) and a comparator (38). Biasing circuit (30) is electrically connected to the integrated circuit voltage supply and the outer epitaxial region (20) of the output vertical pnp transistor (10) for electrically connecting the outer epitaxial region (20) to the voltage supply when the voltage at an output terminal (23) does not exceed the supply voltage and electrically disconnecting the outer epitaxial region (20) from the voltage supply when the voltage at the output terminal (23) exceeds the supply voltage, whereby improper operation of and damage to the integrated circuit upon the occurrence of an external fault condition is at least minimized.

Abstract: A small and easy to fabricate programmable current source correction circuit. The correction circuit consists of a first current division circuit for establishing a reference current; a programmable correction current circuit for establishing the amount of correction current required; a second current division circuit for further reducing the reference current into smaller step or resolution; and a source-sink controlling circuit for determining whether the present invention is to operate as a current sink or current source. The present invention consists of substantially less number of circuit modules and can be fully integrated into a single chip which requires substantially smaller chip area and can operates at a substantially higher frequency compared to prior art.

Abstract: The present invention is a closed-loop peak detection circuit comprising switching means, comparing means, control means, two current sources, and a holding capacitor. The switching means selectively provides one of a plurality of input signals to the comparing means. The control means is coupled to the comparing means. The control means receives first and second control signals for selecting one of three modes: reset, peak detect, and hold. First and second current sources are coupled to the control means. A capacitor is coupled to the first and second current sources for generating an output signal. The output signal is feedback coupled to the comparing means. The comparing means determines when one of the plurality of input signals exceeds the output signal. The control means enables and disables the current sources in response to the comparing means and to the first and second control signals.

Abstract: A feedback circuit (10) for use with a feedback arrangement includes an input terminal (12) for receiving a feedback signal from an output of the feedback arrangement. An output terminal (14) is coupled to a regulating arrangement of the feedback arrangement. A sampling arrangement (16) is coupled to the input terminal for providing a delayed feedback signal. A further arrangement (18,20,22,24,26,28) is coupled to the output terminal (14) for comparing the feedback signal with the delayed feedback signal and with a predetermined reference signal, such that the further arrangement (18,20,22,24,26,28) disables the regulating arrangement if a certain relationship exists between the compared signals.

Abstract: A supply independent bias start-up circuit which is capable of preventing an additional current consumption which may occur therein after the start-up of a supply independent bias circuit thereof, stabilizing a bias voltage even if an input voltage from a power source is varied, and reducing a layout area thereof. The supply independent bias start-up circuit includes a supply independent bias circuit for inputting a voltage from a power source and generating a constant bias voltage, and a start-up circuit for inputting the source voltage, starting up the supply independent bias circuit at the beginning of apply of the source voltage thereto and blocking its own current loop after the source voltage enters a stabilized state.

Abstract: A variable transition time generator has a differential emitter follower circuit that has a push-pull signal at the inputs for driving each end of a timing capacitor. An independently variable timing current source is coupled to each end of the timing capacitor. A differential buffer amplifier passes the voltage across the timing capacitor to an output. A d.c. compensation circuit has a statically biased emitter follower pair of transistors that are driven independently by a pair of variable compensation current sources that track the independently variable timing current sources, the output of which is combined with the output of the buffer amplifier. Also combined with the output of the buffer amplifier is a step correction output derived from the differential input signal. The result is a high speed variable transition time generator that simultaneously produces independently controllable opposite polarity transitions.

Abstract: A first and a second MOS transistor of the same conductivity type are connected in series between a load and a fixed voltage source. The gates of the first and second MOS transistors are connected to sources of input voltage which are of a magnitude smaller than the threshold voltages of the two MOS transistors. The first MOS transistor located next to the load is kept in saturation. A related circuit includes a first and a second MOS transistor of the same conductivity type are connected in series between a load and a fixed voltage source. The first MOS transistor located next to the load is kept in saturation. The gates of the first and second MOS transistors are connected to the gates of third and fourth diode-connected MOS transistors of the same conductivity type as the first and second MOS transistors. The third MOS transistor is connected between a first input current node and fixed voltage source. The fourth MOS transistor is connected between a second input current node and a fixed voltage source.

Abstract: A multiplexer having an enable/disable control circuit which gates the enable/disable control signal with channel select control signals, and the resulting signal is applied to the data input gates, thereby reducing the number of inputs to the data input gates. This simplifies the circuitry and reduces the current requirements, thereby improving response time and reducing signal distortion.

Abstract: A delay circuit for a semiconductor integrated circuit having an unvaried delay time without the deterioration of a signal propagation characteristic under the influence of a voltage source and an ambient temperature.

Abstract: A level and edge sensitive input circuit can recognize a variety of types of input signals on an input line and provide a standard digital logic output for use within the equipment. The input circuit is formed from a bias circuit, two comparators, and a memory bit. The bias circuit applies a bias voltage to the input line. A first comparator inverts the state of the memory bit when the input signals are an increment above the bias voltage. The second comparator clears the state of the memory bit when the input signals are an increment below the bias voltage. In this way, the memory bit cycles through states which provide the desired output signals for use within the equipment.

Abstract: An ECL bandgap reference voltage generator includes a supply-independent current source (14) to produce an output reference voltage (V.sub.BB) that is independent of variations of supply voltage but yet without consuming additional power dissipation. The supply-independent current source (14) is formed of a pair of transistors (Q907, Q908) and first through third resistors (R903, R904, R908).

Abstract: A high frequency switch includes at least two transistors connected in series. By connecting the transistors in series the power handling capability can be increased by a factor of N.sup.2, where N is the number of transistors connected in series. The series is isolated by high impedance resistors and the transistors may be gallium arsenide field-effect transistors.

Abstract: A two-port switched capacitor filter network of the type comprising two input terminals (4, 6), two output terminals (8, 10) and at least three integrator circuits (12, 14, 16) connected therebetween, each integrator circuit including two inputs provided with capacitors which are switched under the control of two disjoint clock states, said integrator circuits being interconnected to constitute a sampling filter having a selected amplitude/frequency response. The two-port network includes two other integrator circuits (36, 38) whose respective inputs are fitted with capacitors switched under the control of two disjoint clock states, said other integrator circuit being interconnected with each other and with the first-mentioned integrator circuits in order to linearize the phase/frequency response of said filter.

Abstract: Supply circuit SC for a Hall sensor multiplication circuit HSC makes it possible to produce both circuits in monolithic technology on a common substrate and yet accomplish the polarity reversal of the output voltage U.sub.H of the multiplication circuit HSC with such accuracy that at said reversal the absolute value of the voltage U.sub.H is preserved with an accuracy of 0.01%.

Abstract: A Darlington output stage is shown in which the saturation voltage is reduced to the level of a single common emitter output transistor. The circuit includes a lateral feed-forward transistor that bridges the driver transistor. A resistor is included to ensure that the driver transistor is turned off when the output transistor saturates. An IC version of the circuit is set forth in detail.

Abstract: An RF signal is transformed (12 and 12') to increase its current component, while reducing its voltage component below the voltage that would damage a GaAs switching device (16 or 16'). The current and voltage transformation are selected so that the power of the RF signal remains substantially constant. Subsequent to the GaAs switching device, the signal is converted (24 and 24') to increase the voltage component while decreasing its current component to substantially recreate the original RF signal.

Abstract: The circuit operates a main switch SCR to pass an a.c. supply V through a load L when a metallic object is in proximity to coil L1. Coil L1 is driven by an oscillator comprising transistor T2 and associated components. SCR is gated on simultaneous occurrence of an output from level detector T3 and a signal from T5, these being ANDed by T4. The timing of the signal from T5 in the supply cycle is governed by the RC time constant of C4,Z1,R14 and is such that the power supplied to the oscillator and level detector is the minimum necessary, for a wide range of supply voltage and load current.