Abstract: A circuit and method for sensing and limiting current. An output driving transistor (M1) is coupled between a circuit output terminal and a power supply terminal. A replicator circuit is formed in a cross-coupled quad configuration from bipolar transistors (Q11, Q12, Q13 and Q14) and is coupled to a second transistor (M2) which generals a voltage proportional to the current flowing in the output driving transistor (M1). The current sensing circuit generates an output current which is proportional to the current flowing in the output driving transistor multiplied by a ratio of the sizes of the second transistor and the output driving transistor. In a current limiting configuration, the output of the cross-coupled quad is used to reset a flip-flop (FF1) that drives the gate terminal of the output transistor (M1), thus shutting down the output transistor before it is damaged due to excess current. The circuitry of the invention may be applied to a high side driver or a low side driver output circuit.

Abstract: In a semiconductor integrated circuit device, a MOS transistor has a relatively high built-in threshold, and in operation, a substrate bias is applied to the MOS transistor so as to cause the MOS transistor to forcibly have a reduced threshold, so that the MOS transistor operates at a high speed with the reduced threshold. When noise is detected, application of the substrate bias is stopped so that the MOS transistor restores the relatively high built-in threshold, and simultaneously, the MOS transistor is put in a standby condition, so that a malfunction can be prevented with the relatively high built-in threshold.

Abstract: Substrate bias control circuitry 100 is provided which includes a bias sensor 101 for measuring a bias voltage of a substrate and generating a control signal and response. A master oscillator 102 is provided for generating a first driving signal, a frequency of the first driving signal adjusted by the control signal generated by the bias sensor 101. A first charge pump 103 is provided for pumping electrons into a substrate in response to the first driving signal. A slave oscillator generates a second driving signal, a frequency of the second driving signal is determined from the frequency of the first driving signal using a phase-locked loop. A second charge pump 105 is provided for pumping electrons into the substrate in response to the second driving signal.

Abstract: A programmable current mirror circuit suitable for incorporation into circuit designs and programmably tailored to produce a ratio of current output over current input based upon the status of a plurality of binary weighted switches. The resulting circuit is readily tailored so as to be insensitive to the "on" characteristics of the switches. Alternatively, the switches may comprise transistors controlled by accompanying circuitry operable to produce an equivalent switching function. An input current divider circuit network formed from an array of current mirrors fractionally divides an input current into a plurality of equivalent currents. A binary weighting circuit receives such fractional input currents, and applies a binary weight to each of same. A voltage to current converter receives the binary weighted voltage and converts the voltage to a weighted output current proportional to the input current directly in relation to the binary weighting applied via the binary weighting circuit.

Abstract: A back bias voltage generator comprising a power-on signal generator for generating a power-on signal when an external voltage remains at a constant level, a reference voltage generator for generating a reference voltage in response to the power-on signal from the power-on signal generator, an internal voltage generator for generating an internal voltage and an internal/external voltage select signal in response to the reference voltage from the reference voltage generator, the internal voltage being constant in level, a back bias voltage sensor for generating an oscillation enable signal in response to the external voltage or the internal voltage from the internal voltage generator under control of the internal/external voltage select signal from the internal voltage generator, an oscillator for generating an oscillating signal at a desired period and an enable signal in response to the oscillation enable signal from the back bias voltage sensor and outputting the generated enable signal to the internal volt

Abstract: In an output circuit, a signal /.phi. opposite in phase to a signal /EN inputted through an input terminal 3 is generated by an inverter 1, and a signal .phi. in phase with the signal /EN is generated by two inverters 8 and 2. When the input signal /EN changes from a high level to a low level, a bipolar NPN transistor 35 is turned on instantaneously to decide an output terminal 5 at the low level forcedly. On the other hand, when the signal /EN changes from the low level to the high level, an NPN transistor 10 is turned on in advance of the other circuits to decide the output terminal 5 at the high level forcedly. Accordingly, it is possible to roughly equalize a delay time (from when the level of the input signal /EN changes at the input terminal 3 to when the level of the signal /.phi. changes at an output terminal 4) to another delay time (to when the level of the signal .phi. changes at the output terminal 5), thus realizing an ideal phase relationship between the two signals/.phi. and .phi.

Abstract: A bootstrap circuit comprising a capacitive device connected between an input line and an output line to boost a signal from the input line, a first voltage supply path being selectively driven in response to a voltage on the output line to transfer or block a supply voltage from a supply voltage source to the output line, a second voltage supply path connected in parallel to the first voltage supply path to transfer or block the supply voltage from the supply voltage source to the output line, and a controller for controlling the second voltage supply path in response to the signal from the input line. According to the present invention, the bootstrap circuit enhances a response speed of an output signal with respect to an input signal. Therefore, the bootstrap circuit can boost the input signal stably and accurately regardless of an impulse noise component.

Abstract: A write data precompensator system is described which comprises a delay element circuit (12) which receives a clock signal and outputs a delayed clock signal which includes a programmable selectable delay in the rising edge of the clock signal. The amount of delay is received using a delay voltage level generated by a delay level circuit (16) which receives delay magnitude control values in digital form. A reference level circuit (18) also generates a continuous level voltage level so that the delay element circuit (12) can instantly change between a delayed operation and an undelayed operation without waiting for the delay voltage level to adjust.

Abstract: The subject of the invention is an integrated delay circuit (10), including two amplifiers (11a, 11b), furnishing different delays, and having a common input, and a control block (12) connected to two terminals of the two amplifiers, respectively, in order to vary the phase offset between the two amplifiers. This circuit is integrated into a III-V semiconductor, such as gallium arsenide.

Abstract: Semiconductor integrated circuits, and more particularly an internal power-supply voltage supplier, can be adapted to high density memory devices, for providing a converted external power-supply voltage as an internal power-supply voltage having a desired potential. An internal power-supply voltage supplier receives a reference signal and an internal power-supply voltage signal and provides a semiconductor integrated circuit with an internal power-supply voltage having a desired voltage level by way of a driver, and comprises an offset generator connected to the driver, including two transistors having different width-length characteristics, for receiving the reference signal and the internal power-supply voltage signal and producing an offset corresponding to the received signals, the internal power-supply voltage is provided at a desired voltage level by the driver when the offset generator performs an offset operation.

Abstract: An integrated detection circuit (10) linearly charges capacitors (14) and (16) over time in response to particular states of an input signal (12). Outputs from the integrated detection circuit (10) are generated by differential pairs (39) when the charge on either of the capacitors (14) or (16) is equal to or greater than a reference voltage input to the differential pairs (39).

Abstract: A page mode/nibble mode dynamic random access memory (DRAM) comprising row and column decoders, the column decoder further comprising a column address buffer and a column address buffer counter. The page mode/nibble mode DRAM also comprises a buffer controller means adapted to receive a write enable signal and to determine whether the DRAM should be placed in a page mode or a nibble mode to facilitate the particular memory access requested by a memory controller. An asserted write enable signal, may indicate, for example, a write operation, thereby calling for the page mode/nibble mode DRAM to move into a page mode to effectuate the write operation. The page mode/nibble mode DRAM also utilizes the write enable signal in the conventional manner, to indicate the initiation of a particular type of memory access, namely a write operation or a read operation.

Abstract: A multiplier in which simplification of a circuit configuration and reduction of a current consumption can be realized. There are provided with first, second, third and fourth pairs of transistors whose capacities are the same with each other and these four pairs are driven by a constant current source, respectively. A sum of first and second input voltage is applied in positive phase to an input end of the first pair and the sum is applied in opposite phase to the other input end thereof. A difference of the first and second input voltages is applied in positive phase to an input end of the second pair and the difference is applied in opposite phase to the other input end thereof. Input ends of the third pair and those of the fourth pair are coupled together to be applied with a direct current voltage.

Abstract: A microwave monolithic integrated circuit (MMIC) RF-generated bias circuit and method includes an input for receiving an RF signal. A rectifier coupled to the input and to electrical ground produces a rectified RF signal in response. A voltage divider coupled to the rectifier and to the electrical ground receives the rectified RF signal and produces a DC voltage therefrom. An output is coupled to the voltage divider for applying the DC voltage to a MMIC field effect transistor (FET) for biasing. No separate bias battery is required, and efficiency is optimized because the generated bias voltage increases to the point where the amplifier voltage begins to decrease, which in turn reduces the generated bias voltage. The derived bias voltage may be used to control other circuits (e.g., other amplifiers, oscillators, mixers, etc.) which require detection of RF presence.

Abstract: A circuit and method in a computer system for generating a power-up reset pulse is disclosed. A specially designed flip-flop and a voltage shifter create a signal that ramps-up with a rising voltage from a newly activated power supply until a desired voltage level is reached. The signal is then deasserted and, in one embodiment, the circuit is reset so that another reset signal can be generated should power be removed and then reapplied in a short period of time. This circuit is configured so that no DC current paths from power to ground exist within the circuit once the reset pulse generation is complete.

Abstract: A current limiting circuit used with voltage regulators or other similar circuits is disclosed. The current limiting circuit uses two transistors, configured as a differential pair, combined with a fixed current source to limit the current available to a pass transistor of the voltage regulator.

Abstract: A vehicle rear view mirror comprising a mirror plate which is provided with a reflection layer and, on the surface facing the viewer of the mirror, is provided with a scratch-resistant protective layer. An adhesive layer which is essentially made of a silicone gel is arranged between the mirror plate and the reflection layer or between the reflection layer and the scratch-resistant protective layer. The silicone gel adhesive layer is formed by an addition cross-linking two-part silicone rubber and exhibits an elasticity which prevents excessive tensions in the mirror layers due to different thermal expansion coefficient of the layers.

Abstract: A power supply circuit disclosed herein includes a three-terminal regulator for stabilizing a positive voltage applied thereto, a voltage converter for converting the stabilized voltage into a negative voltage, a power-supply section for stabilizing a voltage by a light-emitting diode, and a control circuit for applying a bias voltage across a drain and source of a GaAs FET amplifier only when a voltage is being applied across the gate and source of the amplifier. When power is introduced from a power supply, the presence of the negative voltage supplied from the voltage converter is sensed by the control circuit and a bias begins to be applied to the gate. Therefore, when it is sensed that a predetermined voltage is applied to the gate, a bias begins to be applied to the drain of the FET thereafter. When power from the power supply is cut off, a drop in voltage is sensed and the drain bias begins being cut off while the gate bias for the FET is cut off thereafter.

Abstract: A plurality of binary signals each having first and second logic levels respectively representing a binary "1" and a binary "0" and each indicating a binary digit of an individual binary significance cumulatively represent an adjustable delay to be provided by a plurality of delay elements. A first particular number of the binary signals of greatest binary significance are decoded to provide, in a thermometer code, a plurality of signals each having first and second amplitudes. The signals in the thermometer code control the operation of individual switches each having first and second operative relationships to provide respectively for a maximum delay or a minimum delay in an associated one of the delay elements. The binary signals of least binary significance are decoded to produce an analog signal variable between the first and second amplitudes.

Abstract: A reference voltage generator is composed of a first constant-voltage generator consisting of three p-type MOS transistors for generating a first reference voltage Vref for use in the normal operation, which is independent of an external power-supply voltage VCC and of a second constant-voltage generator consisting of two p-type MOS transistors and one n-type MOS transistor for generating a second reference voltage Vrefbi for use in a burn-in acceleration test, which is dependent on VCC. The output of each of the constant-voltage generators is feedbacked to the other constant-voltage generator as its input. Two differential amplifiers and two output drivers output, as an internal reduced voltage Vint, the higher one of Vref and Vrefbi which are outputted from the reference voltage generator.