Patents Examined by Than Nguyen
  • Patent number: 11086556
    Abstract: A backup storage for managing backups of clients includes persistent storage and a backup analyzer. The persistent storage includes the backups, protection policies, and an early deletion schedule. The backup analyzer obtains a request to analyze a protection policy of the protection policies; in response to obtaining the request: obtains backup data information associated with the protection policy; makes a determination, based on the backup data information and the protection policy, that a portion of the backups associated with the protection policies overprotect a client of the clients associated with the protection policy; and modifies the early deletion schedule based on the determination to obtain a modified early deletion schedule.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: August 10, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Asif Khan, Amith Ramachandran, Amarendra Behera, Deepika Nagabushanam, Ashish Kumar, Pati Mohan, Tushar Dethe, Himanshu Arora, Gururaj Soma, Sapna Chauhan, Soumen Acharya, Reshmee Jawed, Shelesh Chopra, Yasemin Ugur-Ozekinci, Navneet Upadhyay, Shraddha Chunekar, Deepak Anantha Bellare Mallya, Arun Chakravarthy, Kanagasabapathy Venkatachalam
  • Patent number: 11086520
    Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: August 10, 2021
    Assignee: Intel Corporation
    Inventors: Mark A. Schmisseur, Mohan J. Kumar, Balint Fleischer, Debendra Das Sharma, Raj K. Ramanujan
  • Patent number: 11073989
    Abstract: Provided are a computer program product, system, and method for using mirror indicators to indicate whether to mirror tracks in a data set in a primary volume mirrored to a secondary volume. A table includes a mirror indicator for each of a plurality of tracks in at least one data set in the primary volume indicating whether a track is to be mirrored to the secondary volume. In response to a write command of write data for one of the tracks in the primary volume, creating a record set in a cache for the primary volume including write data for the track to transfer to the secondary volume in response to the mirror indicator for the track indicating that the track is to be mirrored. The write data in the record set is transferred from the cache to the secondary volume.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: July 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory E. McBride, Dash D. Miller, Miguel A. Perez, David C. Reed
  • Patent number: 11074182
    Abstract: Systems, apparatuses, and methods related to three tiered hierarchical memory systems are described herein. A three tiered hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example apparatus may include a persistent memory, and one or more non-persistent memories configured to map an address associated with an input/output (I/O) device to an address in logic circuitry prior to the apparatus receiving a request from the I/O device to access data stored in the persistent memory, and map the address associated with the I/O device to an address in a non-persistent memory subsequent to the apparatus receiving the request and accessing the data.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Vijay S. Ramesh, Anton Korzh, Richard C. Murphy, Scott Matthew Stephens
  • Patent number: 11074173
    Abstract: A system and a method of managing over-provisioning (OP) on non-volatile memory (NVM) computer storage media including at least one NVM storage device, by at least one processor, may include: receiving a value of one or more run-time performance parameters pertaining to data access requests to one or more physical block addresses (PBAs) of the storage media; receiving at least one of a target performance parameter value and a system-inherent parameter value; analyzing the received at least one run-time performance parameter value, to determine an optimal OP ratio of at least one NVM storage device in view of the received at least of a target performance parameter value and system-inherent parameter value; and limiting storage of data objects on the at least one NVM storage device according to the determined OP ratio.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 27, 2021
    Assignee: Lightbits Labs Ltd.
    Inventor: Abel Alkon Gordon
  • Patent number: 11068197
    Abstract: A variety of applications can include apparatus and/or methods that include tracking data temperatures of logical block addresses for a memory device by operating multiple accumulators by one or more data temperature analyzers to count host writes to ranges of logical block addresses. Data temperature for data written by a host is a measure of how frequently data at a logical block address is overwritten. In various embodiments, tracking can include staggering the start of counting by each of the multiple accumulators to provide subsequent binning of logical block addresses bands into temperature zones, which can achieve better data segregation. Data having a logical block address received from a host can be routed to a block associated with a temperature zone based on the binning provided by the staggered operation of the multiple accumulators by one or more data temperature analyzers. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Peter Sean Feeley, Ashutosh Malshe, Sampath Ratnam, Harish Reddy Singidi, Vamsi Pavan Rayaprolu
  • Patent number: 11061590
    Abstract: A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Tonia G. Morris, Christopher P. Mozak, Christopher E. Cox
  • Patent number: 11055182
    Abstract: In one approach, data blocks or files that have a history of change are tagged for automatic transfer to backup on the assumption that they have changed since the last backup. Other data blocks and files are first tested for change, for example by comparing digital fingerprints of the current data versus the previously backed up data, before transferring to backup.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: July 6, 2021
    Assignee: Rubrik, Inc.
    Inventor: Looi Chow Lee
  • Patent number: 11036626
    Abstract: A system and a method of managing over-provisioning (OP) on non-volatile memory (NVM) computer storage media including at least one NVM storage device, by at least one processor, may include: receiving a value of one or more run-time performance parameters pertaining to data access requests to one or more physical block addresses (PBAs) of the storage media; receiving at least one of a target performance parameter value and a system-inherent parameter value; analyzing the received at least one run-time performance parameter value, to determine an optimal OP ratio of at least one NVM storage device in view of the received at least of a target performance parameter value and system-inherent parameter value; and limiting storage of data objects on the at least one NVM storage device according to the determined OP ratio.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: June 15, 2021
    Assignee: Lightbits Labs Ltd.
    Inventor: Abel Alkon Gordon
  • Patent number: 11030108
    Abstract: In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Berkin Akin, Rajat Agarwal, Jong Soo Park, Christopher J. Hughes, Chiachen Chou
  • Patent number: 11029853
    Abstract: Apparatus and methods of operating solid-state drives in a storage system are described. A method includes adjusting, by a host controller of a storage system during run-time, storage bandwidth for a storage system process responsive to an input output (I/O) write request to write data to the storage system that includes multiple solid-state storage drives by determining an allocation share for the storage system process requesting to write the data, and responsive to determining an open segment usage by the storage system process is under the allocation share for the storage system process, opening a new segment for the storage system process.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 8, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Timothy W. Brennan, Nidhi Pankaj Doshi, Xiaohui Wang
  • Patent number: 11030106
    Abstract: A storage system and method for enabling host-driven regional performance in memory are provided. In one embodiment, a method is provided comprising receiving a directive from a host device as to a preferred logical region of a non-volatile memory in a storage system; and based on the directive, modifying a caching policy specifying which pages of a logical-to-physical address map stored in the non-volatile memory are to be cached in a volatile memory of the storage system. Other embodiments are provided, such as modifying a garbage collection policy of the storage system based on information from the host device regarding a preferred logical region of the memory.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: June 8, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Ramkumar Ramamurthy, Judah Gamliel Hahn
  • Patent number: 11023372
    Abstract: This application relates to example memory reclaim methods and apparatuses, so as to resolve a problem of application stalling easily caused by memory reclaim that is not performed in time. One example method includes monitoring user operation and use information and memory occupation information of applications installed on a terminal. If it is determined, according to at least one of the user operation and use information or the memory occupation information, that a memory reclaim condition is currently met, an application whose memory is to be reclaimed is determined according to the user operation and use information and memory occupation information of applications currently running on the terminal and from the applications currently running. A memory reclaim is performed by invoking a memory reclaim interface provided by a kernel mode.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 1, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Bintian Wang, Xishi Qiu
  • Patent number: 11023332
    Abstract: A file is backed up to a backup system. A first cloud storage provided by a first cloud provider is connected to the backup system and the file is moved to the first cloud storage. Metadata is created at the backup system to reference the file moved to the first cloud storage. A second cloud storage is connected to the backup system. The file is moved from the first cloud storage to the second cloud storage. The metadata at the backup system is updated to reference the file now residing at the second cloud storage.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: June 1, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Jayanth Kumar Reddy Perneti, Rahul Deo Vishwakarma, Kalyan C Gunda
  • Patent number: 11023171
    Abstract: A read operation can be performed to retrieve data of a write unit at a memory sub-system. An indication of a time of the performance of the read operation can be received. Another indication of another time of a performance of a write operation to store the data of the write unit at the memory sub-system can be received. A difference between the time of the performance of the read operation and the another time of the performance of the write operation can be determined. A refresh operation can be performed for the data of the write unit at the memory sub-system based on the difference between the time of the performance of the read operation and the another time of the performance of the write operation.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: June 1, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tingjun Xie, Zhengang Chen
  • Patent number: 11016686
    Abstract: A method and apparatus of bad location management for storage class memory are disclosed. A nonvolatile memory is partitioned into a non-reserved space and a reserved space, which are divided into multiple data units. The health status of the data units in the non-reserved space are classified into multiple classes including a mostly-good class. For host data read, the data from a mostly-good data unit are read and whether the data includes a pointer is checked. If no pointer, the data read are returned as the host data. Otherwise, the data unit pointed by the pointer is read. For data write, the data from a mostly-good data unit are read. If no pointer in the read data, the host data are written into the mostly-good data unit. Otherwise, the host data are written into the data unit in the reserved space pointed by the pointer.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: May 25, 2021
    Assignee: Wolly Inc.
    Inventors: Yu-Ming Chang, Chuen-Shen Bernard Shung
  • Patent number: 11017857
    Abstract: A memory device comprises a block of ranged content-addressable memory (RCAM) including multiple RCAM memory elements, wherein each RCAM memory element is accessed by content that includes two values; a search register configured to store a search value; and logic circuitry coupled to the multiple content-addressable memory elements and the search register. The logic circuitry is configured to: compare the search value of the search register to the two values of each of the multiple RCAM memory elements in parallel; and identify an RCAM memory element according to the comparison.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Christian M Gyllenskog
  • Patent number: 10990524
    Abstract: A memory with a processing in memory architecture and an operating method thereof are provided. The memory includes a memory array, a mode register, an artificial intelligence core, and a memory interface. The memory array includes a plurality of memory regions. The mode register stores a plurality of memory mode settings. The memory interface is coupled to the memory array and the mode register, and is externally coupled to a special function processing core. The artificial intelligence core is coupled to the memory array and the mode register. The plurality of memory regions are respectively selectively assigned to the special function processing core or the artificial intelligence core according to the plurality of memory mode settings of the mode register, so that the special function processing core and the artificial intelligence core respectively access different memory regions in the memory array according to the plurality of memory mode settings.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: April 27, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Frank Chong-Jen Huang, Yung-Nien Koh
  • Patent number: 10990541
    Abstract: A controller controls an operation of a semiconductor memory device. The controller includes a cache buffer, a request analyzer, and a cache controller. The cache buffer stores multiple cache data. The request analyzer generates request information including information on a size of read data to be read. The cache controller determines an eviction policy of the multiple cache data, based on the size of the read data in the request information.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: April 27, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 10983912
    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register specifies a circular address mode for the loop, first and second block size numbers and a circular address block size selection. For a first circular address block size selection the block size corresponds to the first block size number. For a first circular address block size selection the block size corresponds to the first block size number. For a second circular address block size selection the block size corresponds to a sum of the first block size number and the second block size number.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: April 20, 2021
    Assignee: Texas Instruments Incorporated
    Inventor: Joseph Zbiciak