Abstract: A method for transferring memory pages to a first and a second page repository identifies pages in a memory sharing operation for transfer to a first page repository and pages in a memory migration operation for transfer to a second page repository. Pages in the memory migration operation may be prepared for transfer prior to transfer of the pages in the memory sharing operation. Transferring pages in the migration operation may remove the need to transfer pages in the memory sharing operation.

Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.

Abstract: Systems and methods are disclosed for performing wide memory operations for a wide data cache line. In some examples of the disclosed technology, a processor having two or more execution lanes includes a data cache coupled to memory, a wide memory load circuit that concurrently loads two or more words from a cache line of the data cache, and a writeback circuit situated to send a respective word of the concurrently-loaded words to a selected execution lane of the processor, either into an operand buffer or bypassing the operand buffer. In some examples, a sharding circuit is provided that allows bitwise, byte-wise, and/or word-wise manipulation of memory operation data. In some examples, wide cache loads allows for concurrent execution of plural execution lanes of the processor.

Abstract: In one embodiment, a solid state device includes a controller and a non-volatile memory. The non-volatile memory includes a plurality of dies. Each die includes a plurality of planes. A first super-plane-block is structured from a first plane of the plurality of dies. A second super-plane-block is structured from a second plane of the plurality of dies. A plurality of memory operation instructions that, when executed by the controller, cause the controller to receive a first data stream, write the first data stream to the first super-plane-block, receive a second data stream, and write the second data stream to the second super-plane-block.

Abstract: Systems, apparatuses, and methods for dynamically optimizing memory traffic in multi-client systems are disclosed. A system includes a plurality of client devices, a memory subsystem, and a communication fabric coupled to the client devices and the memory subsystem. The system includes a first client which generates memory access requests targeting the memory subsystem. Prior to sending a given memory access request to the fabric, the first client analyzes metadata associated with data targeted by the given memory access request. If the metadata indicates the targeted data is the same as or is able to be derived from previously retrieved data, the first client prevents the request from being sent out on the fabric on the data path to memory subsystem. This helps to reduce memory bandwidth consumption and allows the fabric and the memory subsystem to stay in a low-power state for longer periods of time.

Abstract: A method comprises, at a network adapter of a first device, detecting a write request for storing data in a storage device of the first device, and the write request comprises a first indication for a first storage address of the data in the storage device. The method also comprises, in response to detecting the write request, storing the data at a second storage address in a memory of the network adapter. The method further comprises, storing the first indication in association with a second indication for the second storage address in the memory to enable the storage device to obtain the data. With the above method, by processing and storing data via the controller and the memory of the network adapter, not only a waste of the processor and the memory of the first device is reduced, but also latency of processing commands is decreased.

Abstract: The present disclosure includes apparatuses and methods related to a memory device as the store to pre-resolved instructions. An example apparatus comprises a memory device coupled to a host via a data bus and a control bus. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes sense amplifiers and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of address translated instructions and/or constant data from the host. The memory controller is configured to write the address translated instructions and/or constant data to a plurality of locations in a bank of the memory device in parallel.

Abstract: A common backup and recovery solution is provided for diverse cloud-based services in a productivity suite. The common backup and recovery solution can be configured to interface with an API platform that is associated with the productivity suite to thereby retrieve text-based data that identifies content of the diverse cloud-based services. The common backup and recovery solution can create a backup of the content by storing the text-based data. The common backup and recovery solution can also employ the text-based data to identify and obtain files that form part of the content and then store the files as part of the backup with the text-based data. To perform a recovery, the common backup and recovery solution can employ the text-based data of the backup and content of the files in the backup to send requests to the API platform that will cause the content to be restored.

Abstract: A request to read data from a location associated with a memory component is received. The request is assigned a first tag, the first tag having a first identifier of a first buffer to store data read from the location. The request to read data is determined to collide with an earlier request to write data to the location. The earlier request is assigned a second tag, the second tag having a second identifier of a second buffer to store data to write to the location. An attempt to lock the second tag and the second buffer for the request to read data is made. The request to read data is fulfilled from the second buffer in response to a successful attempt to lock the second tag and the second buffer.

Abstract: A database system includes a database server, a DRAM, a persistent memory, and at least one storage media. The database server includes a cache manager. The DRAM stores a buffer hash table and the persistent memory includes a persistent memory database cache including a plurality of buffers. Buffer content in a buffer is conditionally persisted subsequent to a system initialization event based on the respective buffer satisfying one or more predefined conditions. Each buffer is associated with buffer descriptor values corresponding to a plurality of buffer descriptors. The plurality of buffer descriptors includes a first type of buffer descriptors and a second type of buffer descriptors. Modifications to the buffer hash table are routed to the DRAM, and modifications to the buffer content and modifications to buffer descriptor values corresponding to the first type of buffer descriptors are explicitly flushed to the persistent memory database cache.

Abstract: This application relates to apparatus and methods for automatically determining and providing digital advertisements to targeted users. In some examples, a computing device receives campaign data identifying items to advertise on a website, and generates campaign user data identifying a user that has engaged all of the items on the website. The computing device may then determine a portion of the users based on a relationship between each user and the campaign user data, and may determine user-item values for each of the items for each user of the portion of users, where each user-item value identifies a relational value between the corresponding user and item. The computing device may then identify one or more of the items to advertise to each user of the portion of users based on the user-item values, and may transmit to a web server an indication of the items to advertise for each user.

Abstract: A memory device can be connected to a host through an interface. The memory device includes a nonvolatile memory which includes a plurality of blocks, and a controller which is electrically connected to the nonvolatile memory. In a case where a read command is received from the host, the controller reads first data designated by the read command from a first block of the nonvolatile memory, to transmit the first data to the host, and to write the first data to a second block of the nonvolatile memory instead of the first block.

Abstract: A method includes receiving an indication of an operational mode for a memory system including a set of memory devices. A first memory device of the set of memory devices includes a first media having a first media type and a second memory device of the et of memory devices includes a second media having a second media type that is different than the first media type. The method also includes allocating, by a processing device, a first portion and a second portion of the first memory device based on the operational mode for the memory system. The method also includes storing data at the first portion of the first memory device, the second portion of the first memory device, or the second memory device based on the operational mode for the memory system.

Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. An example method includes receiving a request to store data in a persistent memory device and a non-persistent memory device via an input/output (I/O) device; redirecting the request to store the data to logic circuitry in response to determining that the request corresponds to performance of a hierarchical memory operation; storing in a base address register associated with the logic circuitry, logical address information corresponding to the data responsive to receipt of the redirected request; asserting, by the logic circuitry, an interrupt signal on a hypervisor, the interrupt signal indicative of initiation of an operation to be performed by the hypervisor to control access to the data by the logic circuitry; and writing, based at least in part, on receipt of the redirected request, the data to the persistent memory device and the non-persistent memory device substantially concurrently.

Abstract: A method for managing Logical Block Address (LBA) range overlap checking in a Non-Volatile Memory express (NVMe) based Solid State Drive (SSD) includes detecting, by an LBA-Overlap Check (LOC) module, an overlap between an LBA range of an incoming command with an LBA range of at least one outstanding command in an SSD controller, determining, by the LOC module, an overlap count value corresponding to the incoming command, where the overlap count value indicates occurrence of an overlap between the LBA range of the incoming command and the LBA range of the at least one outstanding command, and executing, by the SSD controller, the incoming command based on the overlap count value corresponding to the incoming command.

Abstract: In one approach, data blocks or files that have a history of change are tagged for automatic transfer to backup on the assumption that they have changed since the last backup. Other data blocks and files are first tested for change, for example by comparing digital fingerprints of the current data versus the previously backed up data, before transferring to backup.

Abstract: Provided are a computer program product, system, and method for managing adding of accessed tracks to a cache list based on accesses to different regions of the cache list. A cache has a least recently used (LRU) end and a most recently used (MRU) end. A determination is made of a high access region of tracks from the MRU end of the cache list based on a number of accesses to the tracks in the high access region. A flag is set for an accessed track, indicating to indicate the accessed track at the MRU end upon processing the accessed track at the LRU end, in response to the determining the accessed track is in the high access region. After the setting the flag, the accessed track remains at a current position in the cache list before being accessed.

Abstract: A storage device includes a storage region in which first data is stored and that is accessed using a first virtual address, and a memory controller configured to control stored data stored in the storage region. The memory controller predicts second data to be accessed using a second virtual address based on the first virtual address, prefetches the second data into an external device, and modifies a physical address mapped to the second virtual address so that the prefetched second data is accessible by a host in communication with the storage device.

Abstract: A memory system comprises a plurality of memory dies and a controller (or other control circuit) connected to the memory dies. To reduce the time it takes for the memory system to program data and make that programmed data available for reading by a host (or other entity), as well as persistently store the data in a compact manner that efficiently uses space in the memory system, the data is concurrently programmed as single bit per memory cell (fast programming) and multiple bits per memory cell (compact storage). To accomplish this programming strategy, the controller concurrently transfers data to be programmed to a first memory die and a second memory die. The transferred data is programmed in the first memory die at a single bit per memory cell and in the second memory die at multiple bits per memory cell.

Abstract: Examples of the present disclosure provide apparatuses and methods related to a translation lookaside buffer in memory. An example method comprises receiving a command including a virtual address from a host translating the virtual address to a physical address on volatile memory of a memory device using a translation lookaside buffer (TLB).