Patents Examined by Than Nguyen
  • Patent number: 11237756
    Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: February 1, 2022
    Assignee: Toshiba Memory Coiporation
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka
  • Patent number: 11237769
    Abstract: According to one embodiment, a controller of a memory system executes a first write operation of writing write data into a first storage region, in response to reception of one or more write requests for specifying a first zone from a host, during a period from execution of an erase operation of the first storage region until a first time elapses. When the first time has elapsed after execution of the erase operation, in a state in which an unwritten region having a size larger than or equal to a first size remains in the first storage region, the controller does not execute the first write operation, allocates the first storage region as a nonvolatile buffer capable of temporarily storing write data to be written to each of a plurality of zones.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: February 1, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11226743
    Abstract: Method and system are provided for managing capacity in a storage system using copy services. The method is a computer-implemented method that predicts an imminent event due to a constrained resource and identifies one or more copy service relationship that will mitigate the imminent event. The method orchestrates a partial or full invalidation of a copy service relationship to reclaim some of the constrained resource to prevent the imminent event, including updating the copy service relationship metadata to indicate the invalidation.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: January 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Dominic Tomkins, Miles Mulholland, Eric John Bartlett, Alex Dicks
  • Patent number: 11226758
    Abstract: Migrating a source volume from a source appliance to a destination appliance, wherein the source volume is assigned to an asymmetric namespace access (ANA) group and initially exposed to a host computer as accessible at the source appliance, includes creating a destination volume on the destination appliance and expanding the ANA group to include the destination volume, with the ANA group initially exposing the destination volume as inaccessible to the host computer at the destination appliance. Subsequently, the destination volume is synchronized to the source volume and then a cutover is performed that includes (i) copying volume metadata including host reservations from the source volume to the destination volume, and (ii) changing the ANA group to expose the source volume as inaccessible at the source appliance and the destination volume as accessible at the destination appliance.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: January 18, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Dmitry Nikolayevich Tylik, Mukesh Gupta, Sathya Krishna Murthy, Marina Shem Tov, Chen Reichbach
  • Patent number: 11221791
    Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving a first write command from a host system; instructing a rewritable non-volatile memory module to perform a first write operation according to the first write command; obtaining first performance information corresponding to the first write operation; and updating threshold information according to the first performance information, wherein the threshold information is configured to determine a type of target data.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: January 11, 2022
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Qi-Ao Zhu, Jing Zhang, Xin Wang, Kai-Di Zhu
  • Patent number: 11216204
    Abstract: A technique maintains multiple copies of data served by storage nodes of a cluster during upgrade of a storage node to ensure continuous protection of the data served by the nodes. The data is logically organized as one or more volumes on storage devices of the cluster and includes metadata that describe the data of each volume. A data protection system may be configured to maintain two copies of the data in the cluster during upgrade to a storage node that is assigned to host one of the copies of the data but that is taken offline during the upgrade. As a result, a slice service of the node may become unavailable during the upgrade. In response to the unavailability of the slice service, the technique redirects replicated data targeted to the slice service to a standby slice service according to a degraded redundant metadata (DRuM) service of the cluster.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: January 4, 2022
    Assignee: NetApp, Inc.
    Inventors: James Philip Wittig, Jared Cantwell, Mark Olson
  • Patent number: 11216366
    Abstract: A memory controller is to store a unique tag at the mid-point address within each of allocated memory portions. In addition to the tag data, additional metadata may be stored at the mid-point address of the memory allocation. For each memory access operation, an encoded pointer contains information indicative of a size of the memory allocation as well as its own tag data. The processor circuitry compares the tag data included in the encoded pointer with the tag data stored in the memory allocation. If the tag data included in the encoded pointer matches the tag data stored in the memory allocation, the memory operation proceeds. If the tag data included in the encoded pointer fails to match the tag data stored in the memory allocation, an error or exception is generated.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: January 4, 2022
    Assignee: Intel Corporation
    Inventors: David M. Durham, Michael LeMay
  • Patent number: 11209991
    Abstract: Disk based emulation of tape libraries is provided with features that allow easier management and administration of a backup system and also allow increased flexibility to both archive data on tape at a remote location and also have fast restore access to archived data files. Features include automatic emulation of physical libraries, and the retention and write protection of virtual tapes that correspond to exported physical tapes.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: December 28, 2021
    Assignee: Overland Storage, Inc.
    Inventors: Victoria Gonzalez, Sergio Encarnacao
  • Patent number: 11200159
    Abstract: The system receives a request to write data and associated metadata. The system determines a key associated with the data, wherein the key corresponds to an entry in a data structure maintained by a first storage system. The system writes the metadata to a first non-volatile memory of a first set of storage drives of the first storage system by updating the entry with a logical block address for the data and a physical location in a second set of storage drives of a second storage system. The system writes the key and the data to a second non-volatile memory of the second set of storage drives based on the physical location, wherein the first non-volatile memory is of a lower density than the second non-volatile memory.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 14, 2021
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 11194727
    Abstract: A computer-implemented method, according to one embodiment, includes: identifying block addresses which are associated with a given object, and combining the block addresses to a first set in response to determining that at least one token is currently issued on one or more of the identified block addresses. A first portion of the block addresses is transitioned to a second set, where the first portion includes ones of the block addresses determined as having a token currently issued thereon. Moreover, a second portion of the block addresses is divided into equal chunks, where the second portion includes the block addresses remaining in the first set. The chunks in the first set are allocated across two or more parallelization units. Furthermore, the block addresses in the second set are divided into equal chunks, and the chunks in the second set are allocated to at least one dedicated parallelization unit.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Amey Gokhale, Ranjith R. Nair, Sandeep R. Patil, Sasikanth Eda
  • Patent number: 11188425
    Abstract: Snapshots may be managed on a data storage system including logical storage unit including data portions. For a first logical storage unit, a first snapshot pointer structure may be provided including entries, each entry corresponding to a physical storage location at which data is stored for a data portion of the first logical storage unit at a particular point in time. A first virtual snapshot lookup table may be provided for a first portion of the first logical storage unit, the first virtual snapshot lookup table including a plurality of entries, each entry corresponding to a respective data portion of the first logical storage unit and including a reference to a respective entry of the first snapshot pointer structure. The virtual lookup table may correspond to multiple snapshots of the first logical storage unit that have a same value for each data portion of the at least first portion.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 30, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Kevin M. Tobin, Andrew L. Chanler, Michael Ferrari, Jeffrey Wilson
  • Patent number: 11182283
    Abstract: One embodiment provides for a non-transitory machine-readable medium storing instructions to cause one or more processors to perform operations comprising receiving an instruction to dynamically allocate memory for an object of a data type and dynamically allocating memory for the object from a heap instance that is specific to the data type for the object, the heap instance including a memory allocator for the data type, the memory allocator generated at compile time for the instruction based on a specification of the data type for the heap instance.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: November 23, 2021
    Assignee: Apple Inc.
    Inventor: Filip J. Pizlo
  • Patent number: 11182074
    Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: November 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shantanu R. Rajwade, Pranav Kalavade, Toru Tanzawa
  • Patent number: 11176040
    Abstract: The present application presents a Uniform Memory Access (UMA) network including a cluster of UMA nodes each having at least one UMA memory unit and a server local to the at least one UMA memory unit. A respective UMA memory unit in a respective UMA node comprises persistent memory; non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the respective UMA node, and a network interface for interfacing with the UMA network. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on the local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: November 16, 2021
    Assignee: Netlist, Inc.
    Inventors: Hyun Lee, Junkil Ryu
  • Patent number: 11163456
    Abstract: Provided are a computer program product, system, and method for using mirror indicators to determine whether to mirror tracks in a data set in a primary volume mirrored to a secondary volume. A table is read. The table is maintained by a primary controller managing the primary volume that includes a mirror indicator for each of a plurality of tracks in at least one data set configured in the primary volume indicating whether a track is to be mirrored to the secondary volume. Record sets are read from a cache of the primary controller for the tracks in primary volume having the mirror indicators in the table indicating that the track is to be mirrored. The write data in the read record sets is applied to tracks in the secondary volume mirroring the tracks in the primary volume.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory E. McBride, Dash D. Miller, Miguel A. Perez, David C. Reed
  • Patent number: 11151033
    Abstract: A processor includes a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is associated with information indicating whether data stored in the cache memory is shared among multiple processor cores.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: October 19, 2021
    Assignee: Tilera Corporation
    Inventors: David M. Wentzlaff, Matthew Mattina, Anant Agarwal
  • Patent number: 11151040
    Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.
    Type: Grant
    Filed: March 24, 2019
    Date of Patent: October 19, 2021
    Assignee: Purdue Research Foundation
    Inventors: Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan
  • Patent number: 11119742
    Abstract: A system for cache efficient reading of column values in a database is provided. In some aspects, the system performs operations including pre-fetching, asynchronously and in response to a request for data in a column store database system, a plurality of first values associated with the requested data. The request may identify a row of the column store database system associated with the requested data. The plurality of first values may be located in the row. The operations may further include storing the plurality of first values in a cache memory. The operations may further include pre-fetching, asynchronously and based on the plurality of first values, a plurality of second values. The operations may further include storing the plurality of second values in the cache memory. The operations may further include reading, in response to the storing the plurality of second values, the requested data from the cache memory.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: September 14, 2021
    Assignee: SAP SE
    Inventor: Thomas Legler
  • Patent number: 11106385
    Abstract: A method, computer program product, and computing system for receiving a request for an application-consistent snapshot of at least a portion of a storage array. A plurality of I/O operations submitted to the at least a portion of the storage array may be monitored. A pre-defined pattern of I/O operations may be identified from the plurality of I/O operations submitted to the storage array. A snapshot of the at least a portion of the storage array may be generated.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: August 31, 2021
    Assignee: EMC IP Holding Company, LLC
    Inventor: Nagasimha Haravu
  • Patent number: 11106365
    Abstract: An aspect of performing flow control of IO in a synchronous replication session between a local storage and a remote storage of a storage system includes tracking an amount of time an input/output (IO) request is processed at the remote storage including an amount of time the IO request is in transmit to and from the remote storage system. The amount of time indicates a remote latency value. An aspect also includes tracking an amount of time the IO request is processed at the local storage and calculating a difference between the remote latency value and the amount of time the IO request is processed at the local storage. The difference indicates a local latency value. An aspect further includes modifying an amount of IO requests admitted at the storage system as a function of the local latency value.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: August 31, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Svetlana Kronrod, Anton Kucherov, Vladimir Shveidel, Xiangping Chen