Abstract: A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

Abstract: Cyclic etch methods comprise the steps of: i) exposing a SiN layer covering a structure on a substrate in a reaction chamber to a plasma of hydrofluorocarbon (HFC) to form a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer, the HFC having a formula CxHyFz where x=2-5, y>z, the HFC being a saturated or unsaturated, linear or cyclic HFC; ii) exposing the polymer layer deposited on the SiN layer to a plasma of an inert gas, the plasma of the inert gas removing the polymer layer deposited on the SiN layer and the modified surface of the SiN layer on an etch front; and iii) repeating the steps of i) and ii) until the SiN layer on the etch front is selectively removed, thereby forming a substantially vertically straight SiN spacer comprising the SiN layer on the sidewall of the structure.

Abstract: A semiconductor device includes a semiconductor substrate having a bonding pad, and a first dielectric layer disposed over the semiconductor substrate. A portion of the bonding pad is exposed by the first dielectric layer. The semiconductor device also includes a metal oxide layer disposed over the portion of the bonding pad, and a wire bond penetrating through the metal oxide layer to bond to the bonding pad. The portion of the bonding pad is entirely covered by the metal oxide layer and the wire bond.

Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.

Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.

Abstract: A semiconductor structure including a self-assembled monolayer for enhancing metal-dielectric adhesion and preventing metal diffusion is provided. The semiconductor structure includes a substrate and a first dielectric layer on the substrate. A contact structure is embedded in the first dielectric layer and includes a conductive line. The semiconductor structure further includes a self-assembled monolayer on the conductive line, and a second dielectric layer on the first dielectric layer and the conductive line. The self-assembled monolayer is chemically bonded to the conductive line and the second dielectric layer.

Abstract: Systems and methods are disclosed herein to provide information to a user based on a communication from a user associated with multiple media assets. Based on the schedule of the media assets, one is selected and recommended to the user.

Abstract: A method of forming a high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.

Abstract: A method includes updating a cloud networking environment from a first network mechanism driver to a second network mechanism driver and identifying a configuration of one or more resources of the cloud networking environment associated with the first network mechanism driver. The method further includes determining one or more features of the configuration of the one or more resources that are incompatible with the second network mechanism driver and updating the one or more features of the configuration of the one or more resources to be compatible with the second network mechanism driver.

Abstract: The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.

Abstract: Methods and devices based on the use of dopant-modulated etching are described. During fabrication, a memory storage element of a memory cell may be non-uniformly doped with a dopant that affects a subsequent etching rate of the memory storage element. After etching, the memory storage element may have an asymmetric geometry or taper profile corresponding to the non-uniform doping concentration. A multi-deck memory device may also be formed using dopant-modulated etching. Memory storage elements on different memory decks may have different taper profiles and different doping gradients.

Abstract: A method of manufacturing a semiconductor device packaging panel is provided. The method includes forming a panel having an active side and a backside. The panel includes a plurality of semiconductor die encapsulated with an encapsulant. An active surface of the semiconductor die is exposed on the active side of the panel. A warpage control carrier is attached onto the backside of the panel. The warpage control carrier includes an electroactive element configured for substantially flattening the panel while a control voltage is applied to the electroactive element.

Abstract: Implementations are described which provide for recipient-based filtering of an event that relates to a topic to which consumers are subscribed. Responsive to determining that an attribute of the event includes a set of one or more identifiers for intended recipients for the event, the event is delivered to consumers that correspond to the intended recipients. Alternatively, responsive to determining that the attribute of the event does not include a set of one or more identifiers for intended recipients for the event, the event is delivered to all of the consumers subscribed to the topic to which the event relates.

Abstract: A request to execute a workload is received from a client device. The request includes identification information associated with one or more containers of multiple containers supported by one or more host systems of multiple host systems, where the one or more containers are to execute the workload. Corresponding communication endpoints associated with the one or more containers are identified in view of the identification information. One or more network connections are configured between the corresponding communication endpoints of the one or more containers and the client device while bypassing configuring other network connections between other containers of the multiple containers and the one or more containers and further network connections between the one or more containers that do not communicate with one another when executing the workload.

Abstract: A method of fabricating a semiconductor device includes providing a substrate including a semiconductor material having a first lattice constant and then patterning the substrate to form a first semiconductor pattern extending in a first direction. A second semiconductor pattern is also formed on and in contact with the first semiconductor pattern. The second semiconductor pattern extends in the first direction and has a second lattice constant that is sufficiently greater than the first lattice constant so that lattice stress is present at an interface between the first semiconductor pattern and the second semiconductor pattern. The second semiconductor pattern is further patterned to define a sidewall of the second semiconductor pattern that extends in a second direction intersecting the first direction. A gate electrode is formed, which extends in the first direction on the second semiconductor pattern.

Abstract: A light source device includes a substrate, a plurality of light sources arranged on the substrate, a light transmissive member arranged over the light sources, and a light-reflecting pattern. The light-reflecting pattern is arranged above or below the light transmissive member such that a thickness and/or a concentration of material of the light-reflecting pattern in a first region directly above one of the light sources is greater than the thickness and/or the concentration of material of the light-reflecting pattern in a second region above a portion between adjacent ones of the light sources.

Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner including polymer; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.

Abstract: A system and a method for media streaming from multiple sources are disclosed. A content requesting client device accesses a server to receive a list of available sources that may include multiple Content Delivery Networks (CDNs) and independent servers. Based on a pre-set criteria, such as the source delivery performance and cost, the client device partitions the content into parts, allocates a source to each part, and simultaneously receives media streams of the content parts from the allocated sources. The server may be a Video-on-Demand (VOD) server, and the content may be a single file of a video data, such as a movie. The delivery performance of the used sources is measured during the streaming for updating the partition or the allocation. The updated measured performance may be stored locally at the client device, or at a server for use by other clients. The client actions may be implemented as a client-side script.

Abstract: Transistors having a control gate isolated from a first region of semiconductor material having a first conductivity type, first and second source/drain regions having a second conductivity type different than the first conductivity type and formed in the first region of semiconductor material, and a second region of semiconductor material having the first conductivity type in contact with the first region of semiconductor material, wherein the first region of semiconductor material is between the control gate and the second region of semiconductor material, wherein the first region of semiconductor material has a first width, and wherein the second region of semiconductor material has a second width, less than or equal to the first width, as well as memory containing such transistors.