Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

Abstract: An encapsulation resin composition is used to hermetically seal a gap between a base member and a semiconductor chip bonded onto the base member. The encapsulation resin composition has a reaction start temperature of 160° C. or less. A melt viscosity of the encapsulation resin composition is 200 Pa·s or less at the reaction start temperature, 400 Pa·s or less at any temperature which is equal to or higher than a temperature lower by 40° C. than the reaction start temperature and which is equal to or lower than the reaction start temperature, and 1,000 Pa·s or less at a temperature lower by 50° C. than the reaction start temperature.

Abstract: A browser on a client device is navigated to a hosting computing system that hosts a service that provides access to documents. The browser is navigated to a particular document, to access the document. The document is displayed by the browser. A link to the document is displayed in an address bar generated by the browser, along with a graphical element indicative of the sharing attributes corresponding to the link.

Abstract: In a described example, an apparatus includes: a process chamber configured for a pressure greater than one atmosphere, having a device chuck configured to support electronic devices that are mounted on package substrates and partially covered in mold compound, the electronic devices spaced from one another by saw streets; and a saw in the process chamber configured to cut through the mold compound and package substrates in the saw streets to separate the molded electronic devices one from another.

Abstract: The present disclosure relates to semiconductor structures, and more particularly, to crackstop structures and methods of manufacture. The structure includes: a die matrix comprising a plurality of dies separated by at least one scribe lane; and a crackstop structure comprising at least one line within the at least one scribe lane between adjacent dies of the plurality of dies.

Abstract: A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.

Abstract: Methods and systems for implementing communications between a Management Controller (MC) and a Network Controller (NC) are disclosed. Embodiments of the present technology may include a method for implementing communications between an MC and an NC that involves establishing Internet Protocol (IP) connectivity between the MC and the NC using Network Controller Sideband Interface (NC-SI) control packets and communicating between the MC and the NC via an NC-SI and the established IP connectivity.

Abstract: A row of backside support pillar structures is formed through a first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers. At least one upper-tier alternating stack can be formed, and memory stack structures can be formed through the alternating stacks. A backside trench can be formed through the alternating stacks selective to the row of backside support pillar structures. The sacrificial material layers are replaced with electrically conductive layers, and the backside trench can be filled with a backside trench fill structure, which includes the row of backside support pillar structures. The row of backside support pillar structures reduces or prevents tilting or collapse of the alternating stacks during replacement of the sacrificial material layers with the electrically conductive layers.

Abstract: A alternating stack of insulating layers and sacrificial material layers is formed over a substrate. An array of memory opening fill structures and an array of support pillar structures are formed through the alternating stack. Backside trenches are formed through the alternating stack by performing an anisotropic etch process. The anisotropic etch process etches peripheral portions of a subset of the array of support pillar structures. The sacrificial material layers are replaced with electrically conductive layer by forming backside recesses while the support pillar structures provide mechanical support to the insulating layers.

Abstract: A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.

Abstract: A data capturing system for use with aerial spherical imagery is provided. The system allows for capturing and tracking of data with respect to those accessing and viewing particular aerial spherical imagery, such as the imagery on a GIS map. The data capturing system may include a server having a processor and a memory and a software application providing instruction to the server to display aerial spherical imagery, such as spherical imagery, to a user through a network connection, such as through the Internet. For example the system may provide the map as a website to the user that is displayed on a remote computing device accessible by the user in order to view the spherical imagery. Data related to the interaction of the user with the website is captured and tracked in order to use such data for other purposes.

Abstract: This disclosure discloses a method of manufacturing a light-emitting device includes steps of providing a first substrate with a plurality of first light-emitting elements and adhesive units arranged thereon, providing a second substrate with a first group of second light-emitting elements and a second group of second light-emitting elements arranged thereon, and connecting the a second group of second light-emitting elements and the adhesive units. The first light-emitting elements and the first group of second light-emitting elements are partially or wholly overlapped with each other during connecting the second group of second light-emitting elements and the adhesive units.

Abstract: A semiconductor device according to an embodiment includes: a bonding substrate which includes a first chip forming portion having first metal pads provided at a semiconductor substrate and a first circuit connected to the first metal pads, and a second chip forming portion having second metal pads joined to the first metal pads and a second circuit connected to the second metal pads and being bonded to the first chip forming portion; and an insulating film which is filled into a non-bonded region between the first chip forming portion and the second chip forming portion at an outer peripheral portion of the bonding substrate. At least a part of the insulating film contains at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide.

Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.

Abstract: A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. In the laser step, a plastic package material covering on each of the cutting streets is removed via a laser beam. In the plating step, a plurality of plating surfaces are disposed on a plurality of areas of the leadframe without the plastic package material. In the singulation step, the cutting streets of the leadframe are cut to form the package structure.

Abstract: A method of processing a semiconductor wafer includes: forming a first metal layer or metal layer stack on a backside of the semiconductor wafer; forming a plating preventative layer on the first metal layer or metal layer stack, the plating preventative layer being formed at least over a kerf region of the semiconductor wafer and such that part of the first metal layer or metal layer stack is uncovered by the plating preventative layer, wherein the kerf region defines an area for dividing the semiconductor wafer along the kerf region into individual semiconductor dies; and plating a second metal layer or metal layer stack on the part of the first metal layer or metal layer stack uncovered by the plating preventative layer, wherein the plating preventative layer prevents plating of the second metal layer or metal layer stack over the kerf region.

Abstract: A method, a device, and a non-transitory storage medium are described in which a deployment and management of composite application service is provided. The service may allow a third party to develop and on-board logic that manages an application service hosted in an application layer network of a network provider. The logic may include optimization of the application service and remedial procedures that address events associated with degradation and/or performance of the application service. The service may configure resources of a host device to host the logic and expose services provided by the network provider in support of the management of the application service.

Abstract: Provided is a method of manufacturing a micro light emitting device array. The method includes forming a display transfer structure including a transfer substrate and a plurality of micro light emitting devices, where the transfer substrate includes at least two first alignment marks; preparing a driving circuit board, the driving circuit board including a plurality of driving circuits and at least two second alignment marks, arranging the display transfer structure and the driving circuit board to face each other so that the at least two first alignment marks and the at least two second alignment marks face one another and bonding the plurality of micro light emitting devices of the display transfer structure to the plurality of driving circuits.

Abstract: A semiconductor device includes a semiconductor die having a front side surface, a backside surface opposite the front side surface and side faces. A backside metallization layer is deposited over the backside surface and projects laterally outwards beyond the side faces. A side face protection layer covers the side faces.

Abstract: A hybrid panel method of (and apparatus for) manufacturing electronic devices, and electronic devices manufactured thereby. As non-limiting examples, various aspects of this disclosure provide a method of manufacturing an electronic device, where the method comprises mounting a plurality of subpanels to a panel, processing the subpanels as a panel, and removing the plurality of subpanels from the panel.