Abstract: A fuel cell component includes an electrode support material made with nanofiber materials of Titania and ionomer. A bipolar plate stainless steel substrate and a carbon-containing layer doped with a metal selected from the group consisting of platinum, iridium, ruthenium, gold, palladium, and combinations thereof.

Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate having formed thereon a sacrificial silicon oxide layer, an interlayer dielectric layer formed over the sacrificial silicon oxide layer, and a dummy gate structure formed over the sacrificial silicon oxide layer and within the interlayer dielectric layer, removing the dummy gate structure to form an opening within the interlayer dielectric layer, and removing the sacrificial silicon oxide layer within the opening to expose the semiconductor substrate within the opening. The method further includes the steps of thermally forming an oxide layer on the exposed semiconductor substrate within the opening, subjecting the thermally formed oxide layer to a decoupled plasma oxidation treatment, and etching the thermally formed oxide layer using a self-saturated wet etch chemistry. Still further, the method includes depositing a high-k dielectric over the thermally formed oxide layer within the opening.

Abstract: The invention discloses a method for manufacturing a dual-layer polysilicon gate. The method includes: depositing silicon nitride on silicon oxide of an integrated circuit to be processed; performing anisotropic etching on the silicon nitride to form sidewalls of silicon nitride on sidewalls of a first layer of polysilicon gate of the integrated circuit to be processed; manufacturing a second layer of polysilicon gate; and rinsing the sidewalls of silicon nitride.

Abstract: A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield.

Abstract: A method of manufacturing a GaN-based film includes the steps of preparing a composite substrate, the composite substrate including a support substrate in which a coefficient of thermal expansion in its main surface is more than 0.8 time and less than 1.0 time as high as a coefficient of thermal expansion of GaN crystal in a direction of a axis and a single crystal film arranged on a main surface side of the support substrate, the single crystal film having threefold symmetry with respect to an axis perpendicular to a main surface of the single crystal film, and forming a GaN-based film on the main surface of the single crystal film in the composite substrate, the single crystal film in the composite substrate being an SiC film. Thus, a method of manufacturing a GaN-based film capable of manufacturing a GaN-based film having a large main surface area and less warpage without crack being produced in a substrate is provided.

Abstract: Methods of forming semiconductor devices are provided. The methods may include forming a gate pattern on an active region of a substrate. The methods may further include performing a deoxidization treatment on the substrate.

Abstract: The present invention relates to an electrically conductive membrane that can be configured to be used in fuel cell systems to act as a hydrophilic water separator internal to the fuel cell, or as a water separator used with water vapor fed electrolysis cells, or as a water separator used with water vapor fed electrolysis cells, or as a capillary structure in a thin head pipe evaporator, or as a hydrophobic gas diffusion layer covering the fuel cell electrode surface in a fuel cell.

Abstract: A method for making a semiconductor epitaxial structure is provided. The method includes growing a substrate having an epitaxial growth surface, placing a carbon nanotube layer on the epitaxial growth surface, epitaxially growing a doped semiconductor epitaxial layer on the epitaxial growth surface. The carbon nanotube layer can be suspended above the epitaxial growth surface.

Abstract: Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough. The voids may be defined by shells of microcapsules. The voids impart the dielectric materials with reduced dielectric constants and, thus, increased electrical insulation properties.

Abstract: A fabrication method for improving surface planarity after tungsten chemical mechanical polishing (W-CMP) is disclosed. The method forms contact holes and dummy patterns by performing two respective photolithography-and-etching processes to ensure that the dummy patterns have a depth smaller than that of the contact holes. Then the method fills tungsten into the contact holes and dummy patterns and removes the redundant tungsten by a W-CMP process. With such a method, difference of wiring density between areas can be reduced by the dummy patterns, and hence a better surface planarity of the contact hole layer can be achieved. Besides, as the dummy patterns are formed in a pre-metal dielectric layer and their depth is well controlled, tungsten filled in the dummy patterns will not contact with the device area below the pre-metal dielectric layer, and thus will not affect the performance of the device.

Abstract: Various embodiments provide methods and systems for making and/or cleaning semiconductor devices. In one embodiment, a semiconductor device can be formed including a metal layer and a photoresist polymer. During formation, the semiconductor device can be cleaned in a cleaning chamber by a first cleaning solution provided from a solution supply device. After this cleaning process, a second cleaning solution containing metal ions and/or polymer residues can be produced and processed in a solution processing device to at least partially remove the metal ions and/or polymer residues to produce a third cleaning solution for re-use. In an exemplary fabrication or cleaning system, the solution processing device may be configured connecting to either an inlet or an outlet of the cleaning chamber. After cleaning, the semiconductor device can be processed to include a metal plug or an interconnect wiring.

Abstract: A method of filling of vias and trenches in a dual damascene structure with a filling comprising copper or copper alloy is provided. An electroless deposition filling of the vias with a via filling comprising copper or copper alloy is provided. A trench barrier layer is formed over the via filling with a trench barrier layer comprising Mn or Al. The trench barrier layer is annealed at a temperature that causes a component of the trench barrier layer to pass into the via filling. The trenches are filled with a trench filling comprising copper or copper alloy.

Abstract: Methods for selectively diffusing dopants into a substrate wafer are provided. A liquid precursor is doped with dopants. The liquid precursor is selected from a group comprising monomers, polymers, and oligomers of silicon and hydrogen. The doped liquid precursor is deposited on a surface of the substrate wafer to create a doped film. The doped film is heated on the substrate wafer for diffusing the dopants from the doped film into the substrate wafer at different diffusion rates to create a heavily diffused region and a lightly diffused region in the substrate wafer. The method disclosed herein further comprises selective curing of the doped film on the surface of the substrate wafer. The selectively cured doped film acts as a diffusion source for selectively diffusing the dopants into the substrate wafer.

Abstract: A method of manufacturing a GaN-based film includes the steps of preparing a composite substrate, the composite substrate including a support substrate in which a coefficient of thermal expansion in its main surface is more than 0.8 time and less than 1.0 time as high as a coefficient of thermal expansion of GaN crystal in a direction of a axis and a single crystal film arranged on a main surface side of the support substrate, the single crystal film having threefold symmetry with respect to an axis perpendicular to a main surface of the single crystal film, and forming a GaN-based film on the main surface of the single crystal film in the composite substrate, the single crystal film in the composite substrate being an SiC film. Thus, a method of manufacturing a GaN-based film capable of manufacturing a GaN-based film having a large main surface area and less warpage without crack being produced in a substrate is provided.

Abstract: A method for fabricating vertical surround gate structures in semiconductor device arrays. The method includes forming pillars separated by vertical and horizontal trenches on a substrate. Forming a gate layer over the pillars and trenches such that the gate layer forms gate trenches in the horizontal trenches. The method includes forming fillers within the gate trenches, and planarizing the gate layer and fillers. The method also includes successively etching a first portion of the gate layer, removing the fillers, and etching a second portion of the gate layer.

Abstract: A method for fabricating vertical surround gate structures in semiconductor device arrays. The method includes forming pillars separated by vertical and horizontal trenches on a substrate. Forming a gate layer over the pillars and trenches such that the gate layer forms gate trenches in the horizontal trenches. The method includes forming fillers within the gate trenches, and planarizing the gate layer and fillers. The method also includes successively etching a first portion of the gate layer, removing the fillers, and etching a second portion of the gate layer.

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a nitrogen-containing lower gate insulating layer on the semiconductor substrate, forming an upper gate insulating layer on the nitrogen containing lower gate insulating layer, forming a lower metal layer on the upper gate insulating layer; and selectively removing the lower metal layer in the first region such that a lower metal layer pattern remains in the second region, wherein the upper gate insulating layer in the first region prevents the lower gate insulating layer in the first region from being etched during removing of the lower metal layer in the first region. A semiconductor device fabricated by the method is also provided.

Abstract: A fuel cell system having an adaptable compressor map and method for optimizing the adaptable compressor map is provided. The method includes the steps of establishing an initial operating setpoint for an air compressor based on the adaptable compressor map; monitoring a surge indicator; adjusting the adaptable compressor map based on the monitored surge indicator; determining a desired operating setpoint based on the adjusted adaptable compressor map; and establishing an adapted operating setpoint for the air compressor based on the adaptable compressor map following the adjustment thereof. The steps are repeated until the adaptable compressor map for the air compressor is optimized.

Abstract: A method for making epitaxial structure is provided. The method includes providing a substrate having an epitaxial growth surface, placing a carbon nanotube layer on the epitaxial growth surface, and epitaxially growing an epitaxial layer on the epitaxial growth surface. The carbon nanotube layer can be a carbon nanotube film drawn from a carbon nanotube array and including a plurality of successive and oriented carbon nanotubes joined end-to-end by van der Waals attractive force therebetween.

Abstract: A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.