Patents Examined by Thanhha Pham
  • Method of fabricating semiconductor devices
    Patent number: 8962422
    Abstract: A method of fabricating a semiconductor device includes etching a substrate to form a field trench defining an active region and a lower gate pattern on the active region, the lower gate pattern including a tunneling insulating pattern and a lower gate electrode pattern, filling a field insulating material in the field trench to form a field region, forming an upper gate pattern on the lower gate pattern, sequentially forming a stopping layer and a buffer layer on the field region and the upper gate pattern, forming a first resistive pattern on the buffer layer of the field region, and forming a second resistive pattern on the buffer layer on the upper gate pattern, forming an interlayer insulating layer covering the first and second resistive patterns, and performing a planarization process to remove a top surface of the interlayer insulating layer and to remove the second resistive pattern.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jun Seong, Jae-Hwang Sim
  • Hole formation method, multilayer wiring, semiconductor device, display element, image display device, and system containing via hole formed by the hole formation method
    Patent number: 8956969
    Abstract: A hole formation method including applying a pillar-forming liquid to a base material, to thereby form a pillar; applying an insulating film-forming material to the base material on which the pillar has been formed, to thereby form an insulating film; removing the pillar to form an opening in the insulating film; and heat treating the insulating film in which the opening has been formed.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: February 17, 2015
    Assignees: Ricoh Company, Ltd., Sijtechnology, Inc.
    Inventors: Yuji Sone, Naoyuki Ueda, Yuki Nakamura, Yukiko Abe, Kazuhiro Murata, Kazuyuki Masuda
  • Method for fabricating a multi-gate device
    Patent number: 8956931
    Abstract: A device includes a wafer substrate including an isolation feature, at least two fin structures embedded in the isolation feature, and at least two gate stacks disposed around the two fin structures respectively. A first inter-layer dielectric (ILD) layer is disposed between the two gate stacks, with a dish-shaped recess formed therebetween, such that a bottom surface of the recess is below the top surface of the adjacent two gate stacks. A second ILD layer is disposed over the first ILD layer, including in the dish-shaped recess. The second ILD includes nitride material; the first ILD includes oxide material.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: February 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
  • Methods of fabricating a semiconductor device including metal gate electrodes
    Patent number: 8946026
    Abstract: A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: February 3, 2015
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Sukhun Choi, Boun Yoon, Jae-Jik Baek, Byung-Kwon Cho
  • Bump-on-trace methods and structures in packaging
    Patent number: 8945984
    Abstract: A method and structure for bump-on-trace bonding is provided. In an embodiment traces to be used for bump-on-trace (BOT) bonding are protected during a pre-solder treatment. The pre-solder treatment improves the adhesion between the exposed traces (e.g., the non-BOT traces) and a solder resist layer.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jiun Yi Wu
  • Replacement gates to enhance transistor strain
    Patent number: 8946016
    Abstract: Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: February 3, 2015
    Assignee: Intel Corporation
    Inventor: Mark T. Bohr
  • Low temperature coefficient resistor in CMOS flow
    Patent number: 8940598
    Abstract: A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: January 27, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Greg Charles Baldwin, Kamel Benaissa, Sarah Liu, Song Zhao
  • In-situ metal gate recess process for self-aligned contact application
    Patent number: 8940597
    Abstract: A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (CMP) processes to planarize the formed gate structure using a CMP tool. An in situ gate etching process is performed in a CMP cleaner of the CMP tool to form a gate recess. A contact etch stop layer (CESL) can then be deposited in the formed gate recess and one or more CMP processes performed to planarize the CESL.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Jung Hsu, Gin-Chen Huang, Yi-An Lin, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann
  • Methods of forming finfet devices with a shared gate structure
    Patent number: 8936986
    Abstract: In one example, the method disclosed herein includes forming a shared sacrificial gate structure above at least one first fin for a first type of FinFET device and at least one second fin for a second type of FinFET device, wherein the second type is opposite to the first type, and forming a first sidewall spacer around an entire perimeter of the sacrificial gate structure in a single process operation.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: January 20, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andy C. Wei, Dae Geun Yang
  • Methods for isolating portions of a loop of pitch-multiplied material and related structures
    Patent number: 8932960
    Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: January 13, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Methods for annealing a contact metal layer to form a metal silicidation layer
    Patent number: 8927423
    Abstract: Methods for annealing a contact metal layer for a metal silicidation process are provided in the present invention. In one embodiment, a method for annealing a contact metal layer for a silicidation process in a semiconductor device includes providing a substrate having a contact metal layer disposed thereon in a thermal annealing processing chamber, providing a heat energy to the contact metal layer in the thermal processing chamber, supplying a gas mixture including a nitrogen gas and a hydrogen gas while providing the heat energy to the contact layer in the thermal processing chamber, wherein the nitrogen gas and the hydrogen gas is supplied at a ratio between about 1:10 and about 1:1, and forming a metal silicide layer on the substrate.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: January 6, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Xinyu Fu, Wei Tang, Kavita Shah, Srinivas Gandikota, San H. Yu, Avgerinos Gelatos
  • Multi-composition dielectric for semiconductor device
    Patent number: 8927359
    Abstract: The present disclosure provides a method of semiconductor device fabrication including forming a multi-composition ILD layer by forming a first portion of an inter-layer dielectric (ILD) layer on a semiconductor substrate; and forming a second portion of an ILD layer on the first portion of the ILD layer. The second portion may have a greater silicon content than the first portion. For example, the second portion may be a silicon rich oxide.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Hao Liu, Chun-Yi Chang, Ming-Feng Lin, Sheng-Wen Yu, Ziwei Fang
  • Microelectronic fabrication methods using composite layers for double patterning
    Patent number: 8921233
    Abstract: Some embodiments provide microelectronic fabrication methods in which a sacrificial pattern is formed on a substrate. A spacer formation layer is formed on the substrate, the spacer formation layer covering the sacrificial pattern. The spacer formation layer is etched to expose an upper surface of the sacrificial pattern and to leave at least one spacer on at least one sidewall of the sacrificial pattern. A first portion of the sacrificial pattern having a first width is removed while leaving intact a second portion of the sacrificial pattern having a second width greater than the first width to thereby form a composite mask pattern including the at least one spacer and a portion of the sacrificial layer. An underlying portion of the substrate is etched using the composite mask pattern as an etching mask.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hwang Sim, Min-chul Kim
  • Integrated circuits with asymmetric pass transistors
    Patent number: 8921170
    Abstract: Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: December 30, 2014
    Assignee: Altera Corporation
    Inventors: Jun Liu, Albert Ratnakumar, Mark T. Chan, Irfan Rahim
  • Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure
    Patent number: 8916933
    Abstract: A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The gate structures for an NFET and a PFET have identically formed sidewalls, and stress materials are provided in recesses in source and drain regions of the NFET and the PFET.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Carl J. Radens
  • Method for manufacturing MOS transistors with different types of gate stacks
    Patent number: 8912067
    Abstract: A method for manufacturing three types of MOS transistors in three regions of a same substrate, including the steps of: forming a first insulating layer, removing the first insulating layer from the first and second regions, forming a silicon oxide layer, depositing an insulating layer having a dielectric constant which is at least twice greater than that of silicon oxide, depositing a first conductive oxygen scavenging layer, removing the first conductive layer from the second and third regions, and annealing.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: December 16, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Luc Huguenin, Grégory Bidal
  • Method for making epitaxial structure
    Patent number: 8906788
    Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A first carbon nanotube layer is placed on the epitaxial growth surface. A first epitaxial layer is epitaxially grown on the epitaxial growth surface. A second carbon nanotube layer is placed on the first epitaxial layer. A second epitaxial layer is epitaxially grown on the first epitaxial layer.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 9, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Method of manufacturing for semiconductor device using expandable material
    Patent number: 8906761
    Abstract: A semiconductor device is manufactured using an expandable material. The method includes forming a first gate insulating layer on a substrate, forming first and second gate structures on the first gate insulating layer, the first and second gate structures being spaced apart from each other at a distance, forming an expandable material on sidewalls and upper surfaces of the first and second gate structures, forming a gap-fill layer on the expandable material between the first and second gate structures, and performing a heat-treatment process to increase the volume of the expandable material.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shinhye Kim, Sangho Rha, Jeong-Kyu Lee, Zulkarnain, Kyungseok Oh, Sangbom Kang, Seungjae Lee, Jungchan Lee
  • Semiconductor device manufacturing method
    Patent number: 8906795
    Abstract: A semiconductor device manufacturing method allows stably forming a plating layer at low cost on one main surface side of a substrate, while preventing unintended plating layer deposition on the other main surface side. Emitter and collector electrodes are respectively formed on the front and back surfaces of a semiconductor substrate. A first film is attached to the back surface. A notch portion of the substrate is filled with a resin member. A second film is attached to an outer peripheral portion of the substrate, straddling the substrate from the front surface to the back surface. The first and second films push out air remaining between the first and second films and the substrate. An electroless plating process is carried out while the first and second films are attached to the substrate, thereby sequentially forming a nickel plating layer and a gold plating layer on the front surface side.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: December 9, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Shoji Sakaguchi, Idayu Sofya
  • Vertical power MOSFET and IGBT fabrication process with two fewer photomasks
    Patent number: 8900943
    Abstract: A process for fabrication of a power semiconductor device is disclosed in which a single photomask is used to define each of p-conductivity well regions and n-conductivity type source regions. In the process a single photomask is deposited on a layer of polysilicon on a wafer, the polysilicon layer is removed from first regions of the power semiconductor device where the p-conductivity well regions and the n-conductivity type source regions are to be formed, and both p-conductivity type and n-conductivity type dopants are introduced into the wafer through the first regions.
    Type: Grant
    Filed: May 31, 2014
    Date of Patent: December 2, 2014
    Assignee: IXYS Corporation
    Inventors: Kyoung Wook Seok, Jae Yong Choi, Vladimir Tsukanov