Abstract: A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole.

Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (?m) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 ?m or less.

Abstract: Methods and apparatus are disclosed for attaching the integrated circuit (IC) packages to printed circuit boards (PCBs) to form smooth solder joints. A polymer flux may be provided in the process to mount an IC package to a PCB. The polymer flux may be provided on connectors of the IC package, or provided on PCB contact pad and/or pre-solder of the PCB. When the IC package is mounted onto the PCB, the polymer flux may cover a part of the connector, and may extend to cover a surface of the molding compound on the IC package. The polymer flux may completely cover the connector as well. The polymer flux delivers a fluxing component that facilitates smooth solder joint formation as well as a polymer component that offers added device protection by encapsulating individual connectors. The polymer component may be an epoxy.

Abstract: The present invention provides some methods for forming at least two different nanowire structures with different diameters on one substrate. Since the diameter of the nanowire structure will influence the threshold voltage (Vt) and the drive currents of a nanowire field effect transistor, in this invention, at least two nanowire structures with different diameters can be formed on one substrate. Therefore, in the following steps, these nanowire structures can be applied in different nanowire field effect transistors with different Vt and drive currents. This way, the flexibility of the nanowire field effect transistors can be improved.

Abstract: A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.

Abstract: Interconnects (34) include an inside interconnect section (40) and an outside interconnect section (41). The inside interconnect section (40) includes a first interconnect layer (42), a second interconnect layer (43), and a connection section (44) that connects the first interconnect layer (42) and the second interconnect layer (43). The outside interconnect section (41) includes a third interconnect layer (45). Of a plurality of interconnects (34), in one interconnect (X) of neighboring interconnects the second interconnect layer (43) and the third interconnect layer (45) are connected, and in another of the neighboring interconnects (Y), the first interconnect layer (42) and the third interconnect layer (45) are connected.

Abstract: An anneal of a gate recess prior to formation of a gate contact, such as a Schottky contact, may reduce gate leakage and/or provide a high quality gate contact in a semiconductor device, such as a transistor. The use of an encapsulation layer during the anneal may further reduce damage to the semiconductor in the gate recess of the transistor. The anneal may be provided, for example, by an anneal of ohmic contacts of the device. Thus, high quality gate and ohmic contacts may be provided with reduced degradation of the gate region that may result from providing a recessed gate structure as a result of etch damage in forming the recess.

Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains.

Abstract: This thin film transistor comprises, on a substrate, at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source-drain electrode, and two or more protective films. The oxide semiconductor layer comprises Sn, O and one or more elements selected from the group consisting of In, Ga and Zn. In addition, the two or more protective films are composed of at least a first protective film that is in contact with the oxide semiconductor film, and one or more second protective films other than the first protective film. The first protective film is a SiOx film having a hydrogen concentration of 3.5 atomic % or lower.

Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package disposed on the first semiconductor package, and a flexible wing interconnection substrate disposed between the first and second semiconductor packages.

Abstract: Integrated circuits and methods of forming the same are provided. An exemplary integrated circuit includes a semiconductor substrate having a central shallow trench isolation (STI) region. A pair of select transistors have drain regions in contact with opposite portions of the central STI region. A central gate structure overlies the central STI region and includes a central gate dielectric layer. The central gate dielectric layer has a medial dielectric region overlying the central STI region, a first lateral dielectric region overlying the first drain region, and a second lateral dielectric region overlying the second drain region. The first lateral dielectric region defines a first programmable element and the second lateral dielectric region defines a second programmable element.

Abstract: A technique of producing a control component for a reflective display device, comprising: forming an array of electronic switching devices; forming over said array of electronic switching devices an insulator region defining a controlled surface topography; and forming on the patterned surface of the insulator region by a conformal deposition technique a substantially planar array of reflective pixel conductors each independently controllable via a respective one of the array of electronic switching devices, wherein each pixel conductor exhibits specular reflection at a range of reflection angles relative to the plane of the array of pixel conductors for a given incident angle relative to the plane of the array of pixel conductors.

Abstract: Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.

Abstract: A display device includes a first electrode, a first insulating layer having a first top surface and a first side wall, the first side wall having a closed shape and being exposed to a first opening reaching the first electrode, an oxide semiconductor layer on the first side wall, the oxide semiconductor layer including a first portion and a second portion, the first portion being connected with the first electrode, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first transparent conductive layer above the first top surface, the first transparent conductive layer being connected with the second portion, and a second transparent conductive layer connected with the first transparent conductive layer, the second transparent conductive layer forming the same layer with the first transparent conductive layer.

Abstract: A method of fabricating a semiconductor device includes: forming a metal layer containing Al; forming an insulating film on the metal layer; forming an opening pattern to the insulating film, the metal layer being exposed in the opening pattern; and forming a wiring layer in the opening pattern, a first portion being disposed between an edge of the wiring layer and an edge of the opening pattern, a width of the first portion being 1 ?m or less, and the metal layer being exposed in the first portion.

Abstract: A structure and a method of fabrication are disclosed of a high voltage junctionless field effect device. A channel layer and a barrier layer are formed sequentially underneath the gate structure. The width of energy band gap of the barrier layer is wider than that of the channel layer. Thus the two dimensional electron gas (2-DEG) generated in the interface between the channel layer and the barrier layer of this junctionless field effect device has higher electron mobility. The structure of the device of this disclosure has a higher breakdown voltage which is advantageous for a high voltage junctionless field device. The structure offers advantages in device performance and reliability.

Abstract: A semiconductor device with multi-level work function and multi-valued channel doping is provided. The semiconductor device comprises a nanowire structure and a gate region. The nanowire structure is formed as a channel between a source region and a drain region. The nanowire structure has a first doped channel section joined with a second doped channel section. The first doped channel section is coupled to the source region and has a doping concentration greater than the doping concentration of the second doped channel section. The second doped channel section is coupled to the drain region. The gate region is formed around the junction at which the first doped section and the second doped section are joined. The gate region has a first work function gate section joined with a second work function gate section. The first work function gate section is located adjacent to the source region and has a work function greater than the work function of the second work function gate section.

Abstract: Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques. Directional ion implantation methods are utilized to selectively modify desired regions of a material layer to improve etch characteristics of the modified material. For example, a modified region of a material layer may exhibit improved etch selectivity relative to an unmodified region of the material layer. Methods described herein are useful for manufacturing 3D hardmasks which may be advantageously utilized in various integration schemes, such as fin isolation and gate-all-around, among others. Multiple directional ion implantation processes may also be utilized to form dopant gradient profiles within a modified layer to further influence etching processes.

Abstract: Provided are atomic layer deposition methods to deposit a tungsten film or tungsten-containing film using a tungsten-containing reactive gas comprising one or more of tungsten pentachloride, a compound with the empirical formula WCl5 or WCl6.

Abstract: An array substrate for LCD devices and a method of manufacturing the same are provided. By using a structure where an empty space is secured in a data line area as in a DRD structure in which the number of data lines is reduced by half, a capacitance is sufficiently secured by forming a sub storage capacitor in the data line area of the empty space, and thus, an area of a main storage capacitor can be reduced. Accordingly, the cost can be reduced, and moreover, an aperture ratio can be enhanced.