Patents Examined by Thanhha Pham
  • Method of manufacturing semiconductor device
    Patent number: 9324570
    Abstract: The present invention provides a method of manufacturing a semiconductor device including using a first photomask to form a sacrificial block on a hard mask layer in a first region, a first dummy pattern on the sacrificial block, a first spacer on sidewalls of the sacrificial block and a second spacer in a second region; using a second photomask to form a feature mask on the first dummy pattern and a fin cutting mask on the second spacer; and performing a fin cutting process to remove a portion of the first dummy pattern, a portion of the sacrificial block underlying the portion of the first dummy pattern and the first spacer to form a feature spacer and to remove a portion of the second spacer without being covered with the fin cutting mask to form a fin spacer.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: April 26, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: En-Chiuan Liou
  • Bipolar transistor with carbon alloyed contacts
    Patent number: 9306042
    Abstract: A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: April 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Bahman Hekmatshoartabari, Tak H. Ning
  • Method of fabricating semiconductor device
    Patent number: 9305788
    Abstract: A method of fabricating a semiconductor device includes: forming a metal layer containing Al; forming an insulating film on the metal layer; forming an opening pattern to the insulating film, the metal layer being exposed in the opening pattern; and forming a wiring layer in the opening pattern, a first portion being disposed between an edge of the wiring layer and an edge of the opening pattern, a width of the first portion being 1 ?m or less, and the metal layer being exposed in the first portion.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: April 5, 2016
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Methods for forming a semiconductor device using masks with non-metallic portions
    Patent number: 9305801
    Abstract: A method of forming a semiconductor device can be provided by forming a mask pattern including non-metallic first spaced-apart portions that extend in a first direction on a lower target layer and non-metallic second spaced-apart portions that extend in a second direction on the lower target layer to cross-over the non-metallic first spaced-apart portions at locations. The lower target layer can be etched using the mask pattern.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: April 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sughyun Sung, Myeongcheol Kim, Myung-Hoon Jung
  • Thin film transistor substrate and method of manufacturing liquid crystal display device using the same
    Patent number: 9293425
    Abstract: A thin film transistor substrate includes pixels disposed in a display area and connected to gate lines and data lines crossing the gate lines, a gate driver disposed in a non-display area adjacent to the display area and connected to the gate lines, signal pad parts disposed in the non-display area and connected to the gate driver and the data lines, test pad parts disposed in a cutting area adjacent to the non-display area and connected to the signal pad parts, static electricity dispersion parts disposed in the cutting area and connected to the plurality of test pad parts, and a guard line disposed in the cutting area and connected to the static electricity dispersion parts. The static electricity dispersion parts disperse a static electricity inflowing from the signal pad parts and the plurality of test pad parts to the guard line.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: March 22, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Byungju Lee, Sijin Kim, Sangah Koh
  • Land structure for semiconductor package and method therefor
    Patent number: 9293398
    Abstract: In one embodiment, a method for forming a package substrate includes selectively removing portions of a lead frame to form cavities and filling the cavities with a resin layer to define an adhesion pad and a land structure. Top portions of the lead frame are selectively removed to isolate the adhesion pad and the land structure from each other, to expose a top surface of the resin layer, and to form at least one land having a part with a relatively greater size than the size of a respective lower part.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: March 22, 2016
    Assignee: Amkor Technology, Inc.
    Inventors: Kyoung Yeon Lee, Byong Jin Kim, Jae Min Bae, Hyung Il Jeon, Gi Jeong Kim, Ji Young Chung
  • Method for removing electroplated metal facets and reusing a barrier layer without chemical mechanical polishing
    Patent number: 9293368
    Abstract: A method for avoiding using CMP for eliminating electroplated copper facets and reusing barrier layer in the back end of line (“BEOL”) manufacturing processes. Electropolishing is employed to remove the deposited surface metal, stopping at the barrier layer to form a smooth surface that may be utilized in subsequent steps. The method is suitable for the electropolishing of metal surfaces after formation of filled vias for through-silicon via processes employing metals such as copper, tungsten, aluminum, or alloys thereof. The remaining barrier layer may be reused to fabricate the redistribution layer.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: March 22, 2016
    Assignee: National Center for Advanced Packaging Co., Ltd.
    Inventors: Kai Xue, Daquan Yu
  • Transistor strain-inducing scheme
    Patent number: 9287398
    Abstract: A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee
  • Methods for depositing films on sensitive substrates
    Patent number: 9287113
    Abstract: Methods and apparatus to form films on sensitive substrates while preventing damage to the sensitive substrate are provided herein. In certain embodiments, methods involve forming a bilayer film on a sensitive substrate that both protects the underlying substrate from damage and possesses desired electrical properties. Also provided are methods and apparatus for evaluating and optimizing the films, including methods to evaluate the amount of substrate damage resulting from a particular deposition process and methods to determine the minimum thickness of a protective layer. The methods and apparatus described herein may be used to deposit films on a variety of sensitive materials such as silicon, cobalt, germanium-antimony-tellerium, silicon-germanium, silicon nitride, silicon carbide, tungsten, titanium, tantalum, chromium, nickel, palladium, ruthenium, or silicon oxide.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: March 15, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Hu Kang, Shankar Swaminathan, Adrien LaVoie, Jon Henri
  • Spacer enabled active isolation for an integrated circuit device
    Patent number: 9269606
    Abstract: A method for forming an active isolation structure in a semiconductor integrated circuit die is disclosed. A first hard mask layer is deposited over a semiconductor substrate. Portions of the first hard mask layer are removed to form at least one trench. A spacer layer is deposited over the first hard mask and extends into each trench to cover exposed portions of the semiconductor substrate surface in each trench. Portions of the spacer layer are removed such that remaining portions define spacer layer walls covering the side walls of each trench. A second hard mask layer is deposited and extends into each trench between opposing spacer layer walls. The spacer layer walls are removed such that remaining portions of the first and second hard mask layers define a mask pattern, which is then transferred to the substrate to form openings in the substrate, which are filled with an isolation material.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: February 23, 2016
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Paul Fest
  • Method of forming bump structure
    Patent number: 9269682
    Abstract: A method of forming a bump structure includes forming a metallization layer on a top metal layer by electroless plating process, forming a polymer layer over the metallization layer; forming an opening on the polymer layer to expose the metallization layer, and forming a solder bump over the exposed metallization layer to make electrical contact with the top metal layer.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Ying-Ju Chen
  • Integrated circuit devices including finFETs and methods of forming the same
    Patent number: 9263521
    Abstract: Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: February 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Jong Jeong, Jeong-Yun Lee, Shi Li Quan, Dong-Suk Shin, Si-Hyung Lee
  • Semiconductor structure having buried conductive elements
    Patent number: 9263454
    Abstract: Embodiments for the present invention provide a semiconductor device and methods for fabrication. In an embodiment of the present invention, a semiconductor structure comprises a first conductor horizontally formed on a semiconductor substrate. A second conductor is vertically formed in a semiconductor stack that includes the semiconductor substrate. An oxidized region is formed proximate to the first conductor. The second conductor is formed in a manner to be in electrical communication with the first conductor. The first conductor is formed in a manner to be laterally connected to the second conductor. The first conductor is formed in a manner to not traverse beneath the oxidized region. The first conductor is formed in a manner to have a reduced link-up resistance with adjacent epitaxial material included in the semiconductor structure.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Pooja R. Batra, Kangguo Cheng, Ramachandra Divakaruni, Johnathan E. Faltermeier, Reinaldo A. Vega
  • Methods of fabricating semiconductor devices with electrode support patterns
    Patent number: 9263536
    Abstract: Methods include sequentially forming a first mold film, a first support film, a second mold film, and a second support film on a substrate, forming a contact hole through the second support film, the second mold film, the first support film and the first mold film, forming an electrode in the contact hole, and removing portions of the second support film, the second mold film and the first mold film to leave a portion of the first support film as a first support pattern surrounding the electrode and to leave a portion of the second support film as a second support pattern surrounding the electrode.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: February 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Gun Kim, Young-Min Ko, Kwang-Tae Hwang
  • Semiconductor structure having interfacial layer and high-k dielectric layer
    Patent number: 9245970
    Abstract: A semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an interfacial layer over the semiconductor substrate, the interfacial layer having a capacitive effective thickness of less than 1.37 nanometers (nm). The semiconductor structure further includes a high-k dielectric layer over the interfacial layer.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: January 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Liang-Gi Yao, Chun-Hu Cheng, Chen-Yi Lee, Jeff J. Xu, Clement Hsingjen Wann
  • Semiconductor structure having buried conductive elements
    Patent number: 9245892
    Abstract: Embodiments for the present invention provide a semiconductor device and methods for fabrication. In an embodiment of the present invention, a semiconductor structure comprises a first conductor horizontally formed on a semiconductor substrate. A second conductor is vertically formed in a semiconductor stack that includes the semiconductor substrate. An oxidized region is formed proximate to the first conductor. The second conductor is formed in a manner to be in electrical communication with the first conductor. The first conductor is formed in a manner to be laterally connected to the second conductor. The first conductor is formed in a manner to not traverse beneath the oxidized region. The first conductor is formed in a manner to have a reduced link-up resistance with adjacent epitaxial material included in the semiconductor structure.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: January 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Pooja R. Batra, Kangguo Cheng, Ramachandra Divakaruni, Johnathan E. Faltermeier, Reinaldo A. Vega
  • Method of manufacturing a semiconductor integrated circuit device
    Patent number: 9240330
    Abstract: The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: January 19, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Takeda, Takao Kumihashi, Hiroshi Yanagita, Takashi Takeuchi, Yasushi Matsuda
  • Method for creating self-aligned transistor contacts
    Patent number: 9236437
    Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mark A. Zaleski, Andy Chih-Hung Wei, Jason E. Stephens, Tuhin Guha Neogi, Guillaume Bouche
  • Methods for depositing fluorine/carbon-free conformal tungsten
    Patent number: 9230815
    Abstract: Provided are atomic layer deposition methods to deposit a tungsten film or tungsten-containing film using a tungsten-containing reactive gas comprising one or more of tungsten pentachloride, a compound with the empirical formula WCl5 or WCl6.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: January 5, 2016
    Assignee: Appled Materials, Inc.
    Inventors: Xinyu Fu, Srinivas Gandikota, Avgerinos V. Gelatos, Atif Noori, Mei Chang, David Thompson, Steve G. Ghanayem
  • Active layer ion implantation method and active layer ion implantation method for thin-film transistor
    Patent number: 9230811
    Abstract: Disclosed are an active layer ion implantation method and an active layer ion implantation method for thin-film transistor. The active layer ion implantation method comprises: applying a photoresist on the active layer; and implanting ions into the active layer through the photoresist.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: January 5, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Zhanjie Ma