Abstract: A method of reducing a migration of oxygen into a high-k dielectric layer of a semiconducting device is disclosed. An oxide layer of the semiconducting device is deposited on a substrate. A chemical composition of a top portion of the oxide layer is altered. The high-k dielectric layer is deposited on the top portion of the oxide layer to form the semiconducting device. The altered chemical composition of the top portion of the oxide layer reduces migration of oxygen into the high-k dielectric layer.

Abstract: A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.

Abstract: A semiconductor device includes a substrate, a first doped well disposed in the substrate, a second doped well disposed in the substrate adjacent to a first side of the first doped well, a buffer region disposed in the first doped well adjacent to a second and opposite side of the first doped well, a gate structure disposed above the first side of the first doped well and extending along a first horizontal direction, a first contact region disposed in the buffer region toward the second side of the first doped well, a second contact region disposed in the buffer region adjacent to the first contact region, and a doped region disposed in the buffer region under the first contact region.

Abstract: A method and structure for bump-on-trace bonding is provided. In an embodiment traces to be used for bump-on-trace (BOT) bonding are protected during a pre-solder treatment. The pre-solder treatment improves the adhesion between the exposed traces (e.g., the non-BOT traces) and a solder resist layer.

Abstract: A method of manufacturing a semiconductor device includes providing a wafer, grinding a backside of the wafer, disposing a backside film on the backside of the wafer, cutting the wafer to singulate a plurality of dies from the wafer, and forming a mark on the backside film disposed on each of the plurality of dies by a laser operation.

Abstract: A method including forming a buffer layer between a top pad layer and a bottom pad layer all above a deep trench capacitor embedded in a substrate, forming a fin pattern, defined by one or more sidewall spacers, above the top pad layer using a sidewall image transfer technique, transferring the fin pattern into the top pad layer stopping of the buffer layer, and forming a fin in direct contact with a strap by transferring the fin pattern into the buffer layer, into the bottom pad layer, and into the substrate and an inner electrode of the deep trench capacitor, the fin is formed from a portion of the substrate and the strap is formed from a portion of the inner electrode of the deep trench capacitor.

Abstract: An array substrate for LCD devices and a method of manufacturing the same are provided. By using a structure where an empty space is secured in a data line area as in a DRD structure in which the number of data lines is reduced by half, a capacitance is sufficiently secured by forming a sub storage capacitor in the data line area of the empty space, and thus, an area of a main storage capacitor can be reduced. Accordingly, the cost can be reduced, and moreover, an aperture ratio can be enhanced.

Abstract: A semiconductor device includes a substrate, a first layer over the substrate, a second layer over the first layer, and a third layer over the second layer. The third layer has a first portion and a second portion. The first portion of the third layer is separated from the second portion of the third layer. The semiconductor device also includes a first blended region beneath the first portion of the third layer. The first blended region includes aluminum atoms drawn from the first layer into at least the second layer. The semiconductor device further includes a second blended region beneath the second portion of the third layer. The second blended region includes aluminum atoms drawn from the first layer into at least the second layer. The semiconductor device also includes a source contact and a drain contact.

Abstract: Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region.

Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.

Abstract: A manufacturing method of an array substrate, comprising the following steps: S1: forming a pattern comprising a semiconductor layer (2), a gate insulating layer (4), a gate electrode (5) and a gate line on a substrate (1); S2: on the substrate (1) subjected to the step S1, forming a metal diffusion layer (3) on the pattern of the semiconductor layer (2) which is not covered by the gate insulating layer (4) and forming a barrier layer (6) in other regions; S3: forming a passivation layer (7) on the substrate (1) subjected to the step S2; and S4: forming a pattern of via holes (11), source and drain electrodes (81, 82), a data line and a pixel electrode (9) on the passivation layer (7), the source and drain electrodes (81, 82) being which being connected to the metal diffusion layer (3) through the via holes (11) respectively. With this method, the process flow is simplified, and the process costs are reduced.

Abstract: A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers which are electrically connected to the electrodes and which cover the top surfaces of the protrusions. A method for manufacturing the semiconductor device includes a step of applying a layer of the resin to the semiconductor device except for the electrodes, a step of patterning the conductive layers on the electrodes and the layer of the resin in accordance with the protrusions, and a step of removing the layer of the resin located between the conductive layers by the use of the patterned conductive layers as masks so as to form the protrusions.

Abstract: A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.

Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metal interconnect layer. The method is performed by depositing one or more self-assembled monolayers on a semiconductor substrate to define a metal interconnect layer area. A metal interconnect layer having a plurality of metal structures is formed on the semiconductor substrate within the metal interconnect layer area. An inter-level dielectric layer is then formed onto the surface of the semiconductor substrate in areas between the plurality of metal structures.

Abstract: A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the gate in the substrate. The drain region includes a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region. The first conductivity type and the second conductivity type are complementary to each other. The semiconductor device further includes a first well region formed under the first doped region, a second well region formed under the second doped region, and a third well region formed under the third doped region. The first well region, the second well region, and the third well region all include the first conductivity type. A concentration of the second well region is different from a concentration of the third well region.

Abstract: In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer. Thus, the p type SiC layer can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer from remaining on the side surface of the trench.

Abstract: Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.

Abstract: According to embodiments of the present invention, a method for forming an optical modulator is provided. The method includes providing a substrate, implanting dopants of a first conductivity type into the substrate to form a first doped region, implanting dopants of a second conductivity type into the substrate to form a second doped region, wherein a portion of the second doped region is formed over and overlaps with a portion of the first doped region to form a junction between the respective portions of the first doped region and the second doped region, and wherein a remaining portion of the second doped region is located outside of the junction, and forming a ridge waveguide, wherein the ridge waveguide overlaps with at least a part of the junction.

Abstract: A method includes followings operations. A substrate including a first surface and a second surface is provided. The substrate and a transparent film are heated to attach the transparent film on the first surface. A first coefficient of a thermal expansion (CTE) mismatch is between the substrate and the transparent film. The substrate and the transparent film are cooled. A polymeric material is disposed on the second surface. A second CTE mismatch is between the substrate and the polymeric material. The second CTE mismatch is counteracted by the first CTE mismatch.

Abstract: A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a source/drain structure over a substrate and forming a metal layer on the source/drain structure. The method for manufacturing a semiconductor structure further includes reacting a portion of the metal layer with the source/drain structure to form a metallic layer on the source/drain structure. The method for manufacturing a semiconductor structure further includes removing an unreacted portion of the metal layer on the metallic layer by an etching process. In addition, the etching process includes using an etchant including HF and propylene carbonate, and the volume ratio of HF to propylene carbonate in the etchant is in a range from about 1:10 to about 1:10000.