Abstract: The present invention is directed to a flexible backplane for direct drive display devices and methods for its manufacture. The flexible backplane has many advantages. Because there is no need for a polyimide layer and only one layer of metal foil is used, the backplanes may be manufactured at a relatively low cost.

Abstract: A device for the extraction and collection of volatiles from soil or planetary regolith. The device utilizes core drilled holes to gain access to underlying volatiles below the surface. Microwave energy beamed into the holes penetrates through the soil or regolith to heat it, and thereby produces vapor by sublimation. The device confines and transports volatiles to a cold trap for collection.

Abstract: A solid-state imaging device is provided. The solid-state imaging device includes: pixels arrayed; a photoelectric conversion element in each of the pixels; a read transistor for reading electric charges photoelectrically-converted in the photoelectric conversion elements to a floating diffusion portion; a shallow trench element isolation region bordering the floating diffusion portion; and an impurity diffusion isolation region for element isolation regions other than the shallow trench element isolation region.

Abstract: Methods and apparatuses relating to large scale FET arrays for analyte detection and measurement are provided. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes.

Abstract: Embodiments of the present invention pertain to the formation of microelectronic structures. Low k dielectric materials need to exhibit a dielectric constant of less than about 2.6 for the next technology node of 32 nm. The present invention enables the formation of semiconductor devices which make use of such low k dielectric materials while providing an improved flexural and shear strength integrity of the microelectronic structure as a whole.

Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.

Abstract: A method for in situ determination of a material composition of optically thin layers deposited from a vapor phase onto a substrate includes irradiating the substrate with incoherent light of at least three different wavelengths, optically detecting in a spatially resolved manner a reflection intensity of a diffuse or a direct light scattering emanating from a deposited layer outside of a total reflection, concurrently providing numerical values of the detected reflection intensity to an optical layer model based on general line transmission theory, ascertaining values for the optical layer parameters of the deposited layer from the optical layer model for the at least three different wavelengths by numerically adapting the optical layer model to a time characteristic of the detected reflection intensities, and quantitatively determining a material composition of the deposited layer from the ascertained values by comparing the ascertained values to standard values.

Abstract: Processes for curing silicon based low k dielectric materials generally includes exposing the silicon based low k dielectric material to ultraviolet radiation in an inert atmosphere having an oxidant in an amount of about 10 to about 500 parts per million for a period of time and intensity effective to cure the silicon based low k dielectric material so to change a selected one of chemical, physical, mechanical, and electrical properties and combinations thereof relative to the silicon based low k dielectric material prior to the ultraviolet radiation exposure. Also disclosed herein are silicon base low k dielectric materials substantially free of sub-oxidized SiO species.

Abstract: An integrated circuit package includes an integrated circuit with one or more on-chip inductors. A package cover covers the integrated circuit. A magnetic material is provided between the integrated circuit and the package cover. The magnetic material may be a soft magnetic thin film. The magnetic material may be affixed to the package cover by an adhesive. The magnetic material may be formed directly on the package cover by one of deposition, sputtering or spraying. The magnetic material may be affixed to the integrated circuit.

Abstract: The present invention provides a semiconductor component having a joint structure including a semiconductor device, an electrode disposed opposite the semiconductor device, and a joining material which contains Bi as main component and connects the semiconductor device to the electrode. Since the joining material contains a carbon compound, joint failure due to the difference in linear expansion coefficient between the semiconductor device and the electrode can be reduced compared with conventional materials. The joining material which contains Bi as main component enables provision of a joint structure in which a semiconductor device and an electrode are joined by a joint more reliable than a conventional joint.

Abstract: The present invention provides silicon nanostructures and their producing method. By employing a metal-assisted chemical etching method, the bottom of the produced silicon nanostructures, connected to the silicon substrate, is porous and side etched, such that the silicon nanostructures can be easily transferred to a hetero-substrate by a physical manner.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: A method for producing an electronic component of a VQFN (very thin quad flat pack no-lead) design includes the following method steps: anchoring at least one integrated circuit element on a sacrificial substrate; contact-connecting the at least one integrated circuit element to the sacrificial substrate with formation of contact-connecting points on the sacrificial substrate; forming an encapsulation on a top side of the sacrificial substrate, the at least one anchored integrated circuit element being mounted on the top side of the sacrificial substrate; removing the sacrificial substrate, thereby uncovering a portion of the contact-connecting points on the underside of the encapsulation.

Abstract: A wafer level integration module and method for fabricating are disclosed according to a construction whereby semiconductor functional device fabrication is carried out only after interconnect structures are processed on a bare wafer. The fabrication and processing include forming interconnect structures in a first side of a wafer. An insulation layer is deposited on the first side of the wafer. A conductive layer is deposited on the insulation layer so as to fill the interconnect structures and contact the insulation layer on the walls thereof. The conductive layer on the interconnect structures forms interconnection contacts on the first side of the wafer and interconnection vias extending into the wafer. The conductive layer including the interconnection contacts is exposed on the first side of the wafer. A semiconductor functional device is fabricated on the first side of the wafer and interconnected with the interconnection contacts during the fabricating.

Abstract: Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.

Abstract: The present invention provides a method of fabricating a semiconductor substrate and a method of fabricating a light emitting device. The method includes forming a first semiconductor layer on a substrate, forming a metallic material layer on the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer and the metallic material layer, wherein a void is formed in a first portion of the first semiconductor layer under the metallic material layer during formation of the second semiconductor layer, and separating the substrate from the second semiconductor layer by etching at least a second portion of the first semiconductor layer using a chemical solution.

Abstract: Provided is a method of forming and/or using a backside-illuminated sensor including a semiconductor substrate having a front surface and a back surface. A transfer transistor and a photodetector are formed on the front surface. The gate of the transfer transistor includes an optically reflective layer. The gate of the transfer transistor, including the optically reflective layer, overlies the photodetector. Radiation incident the back surface and tratversing the photodetector may be reflected by the optically reflective layer. The reflected radiation may be sensed by the photodetector.

Abstract: A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.

Abstract: An image sensor includes at least one photosensitive element disposed in a semiconductor substrate. Metal conductors may be disposed on the semiconductor substrate. A filter may be disposed between at least two individual metal conductors and a micro-lens may be disposed on the filter. There may be insulator material disposed between the metal conductors and the semiconductor substrate and/or between individual metal conductors. The insulator material may be removed so that the filter may be disposed on the semiconductor substrate.

Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.