Abstract: An LED base plate enabling the LED to emit high luminance white light. The base plate has a reflective surface, and protrusions disposed on the reflective surface have top portions formed with curved surfaces. The protrusions have bottom widths of 2 to 4 micrometers and heights of 1.2 to 1.8 micrometers, with adjacent protrusions having spaces of 0.6 to 3 micrometers. An InGaN epitaxy layer is coated on the reflective surface of the base plate and emits ultraviolet of wavelength in the range of 380 to 410 nanometer when the InGaN epitaxy layer is electrified. Ultraviolet light reflected by the reflective surface of the base plate and the protrusions stimulates and mixes fluorescent compounds of zinc oxide and yttrium aluminum garnet to generate complementary light of ultraviolet light. High luminance white light scatteringly emitted is used for illumination.

Abstract: Methods of forming a semiconductor structure including a semiconductor nanowire or epitaxial semiconductor material which extends from at least a surface of source region and the drain region are provided. The methods include converting an upper portion of the source region and the drain region and the semiconductor nanowire or epitaxial semiconductor material into a continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each of the source region and the drain region, and a vertical pillar portion extending upwardly from the lower portion.

Abstract: SiO2 layers are used as adhesion layers in the case of optoelectronic components. Durable adhesions can be produced with silicone rubbers. These materials normally have only an insufficient adhesive strength on materials as frequently used for optoelectronic components, such as LED modules. This then leads in further consequence to a clear reduction of the operating life of the manufactured components. These restrictions are avoided effectively by the use of the adhesion layers, endurance upon operation in damp surroundings and upon temperature change loading is substantially improved.

Abstract: In an optical semiconductor device including an epitaxially-grown light emitting semiconductor layer and a reflective electrode layer provided at a counter face of the light emitting semiconductor layer opposing a light extracting face thereof, a support electrode layer is provided between the reflective electrode layer and the counter face of the light emitting semiconductor layer and is adapted to support the light emitting semiconductor layer and electrically connect the light emitting semiconductor layer to the reflective electrode layer. Also, a total area of the support electrode layer is smaller than an area of the reflective electrode layer. Further, an air gap at a periphery of the support electrode layer and the reflective electrode layer serves as a reflective mirror.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.

Abstract: A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A super-junction structure is disposed within the drift region between the gate and the drain region.

Abstract: The present invention is directed to an MIS type semiconductor device, including a channel layer between a semiconductor body region and a gate insulating film, the channel layer having an opposite semiconductor polarity to that of the semiconductor body region. Since Vfb of the semiconductor device is equivalent to or less than a gate rated voltage Vgcc? of the semiconductor device with respect to an OFF-polarity, density of carrier charge that is induced near the surface of the semiconductor body region is kept at a predetermined amount or less with a guaranteed range of operation of the semiconductor device.

Abstract: A device comprises a heater, a dielectric layer, a phase-change element, and a capping layer. The dielectric layer is disposed at least partially on the heater and defines an opening having a lower portion and an upper portion. The phase-change element occupies the lower portion of the opening and is in thermal contact with the heater. The capping layer overlies the phase-change element and occupies the upper portion of the opening. At least a fraction of the phase-change element is operative to change between lower and higher electrical resistance states in response to an application of an electrical signal to the heater.

Abstract: Systems, methods, and apparatus for linking machine stators are provided. A bracket may be utilized to link adjacent stators within a machine, for example, a turbine. The bracket may include a body portion, a first plurality of extensions, and a second plurality of extensions. The body portion may include a first edge operable to align with a base of a first stator and a second edge opposite the first edge and operable to align with a base of a second stator. The first plurality of extensions may extend from the first edge and may be operable to align with at least one corresponding groove on the base of the first stator. The second plurality of extensions may extend from the second edge and may be operable to align with at least one corresponding groove on the base of the second stator. When utilized to link the first stator and the second stator, the bracket may facilitate a reduction of vibrations in the first stator and the second stator.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: A test pattern for measuring semiconductor alloys using X-ray diffraction (XRD) includes a first region to an Nth region defined on a wafer, and a plurality of test structures positioned in the first region and so forth up to in the Nth region. The test structures in the same region have sizes identical to each other and the test structures in different regions have sizes different from each other.

Abstract: An object is to manufacture and provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which a semiconductor layer including a channel formation region serves as an oxide semiconductor film, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed after an oxide insulating film serving as a protective film is formed in contact with an oxide semiconductor layer. Then, the impurities such as moisture, which exist not only in a source electrode layer, in a drain electrode layer, in a gate insulating layer, and in the oxide semiconductor layer but also at interfaces between the oxide semiconductor film and upper and lower films which are in contact with the oxide semiconductor layer, are reduced.

Abstract: Arrays of memory cells are described along with devices thereof and method for manufacturing. Memory cells described herein include memory elements comprising programmable resistive material and self-aligned bottom electrodes. In preferred embodiments the area of the memory cell is 4F2, F being the feature size for a lithographic process used to manufacture the memory cell, and more preferably F being equal to a minimum feature size. Arrays of memory cells described herein include memory cells arranged in a cross point array, the array having a plurality of word lines and source lines arranged in parallel in a first direction and having a plurality of bit lines arranged in parallel in a second direction perpendicular to the first direction.

Abstract: A vertical type semiconductor device including a first vertical semiconductor device on a semiconductor substrate, a second vertical semiconductor device on the first vertical semiconductor device, and an interconnection between the first and second vertical semiconductor devices.

Abstract: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract: A unit pixel of a photo detecting apparatus includes a photogate, a transfer gate and a floating diffusion region. The photogate includes a junction gate extending in a first direction and a plurality of finger gates extending from the junction gate in a second direction substantially perpendicular to the first direction. The transfer gate is formed adjacent to the junction gate. The floating diffusion region is formed adjacent to the first transfer gate.

Abstract: A semiconductor device includes active regions separated by a trench, a separation layer dividing the trench, and buried bit lines buried in the trench with the separation layer interposed between the buried bit lines.

Abstract: A probe comprises: contact parts to be electrically connected to input/output terminals of an IC device built in a semiconductor wafer under test; interconnect parts at the front ends of which the contact parts are provided; a plurality of beam parts on the top surface of which the interconnect parts are provided along the longitudinal direction; and a base part supporting the plurality of beam parts all together in a cantilever fashion, the beam parts are supported by the base part at a rear end region of the beam parts, and grooves are provided between the adjoining beam parts in the rear end region.

Abstract: Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a plurality of electrically isolated, multi-tiered metal spacers on a front side of a first microelectronic die, and attaching a back-side surface of a second microelectronic die to individual metal spacers. In another embodiment, the method of manufacturing the microelectronic device may further include forming top-tier spacer elements on front-side wire bonds of the first die.