Abstract: An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.

Abstract: A semiconductor device includes a resistance variable element including a free magnetic layer, a tunnel barrier layer and a pinned magnetic layer; and a magnetic correction layer disposed over the resistance variable element to be separated from the resistance variable element, and having a magnetization direction which is opposite to a magnetization direction of the pinned magnetic layer.

Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad. A method of forming a surface mounting component or a chip scale package assembly wherein the component or assembly has at least two different types of solder bumps.

Abstract: Provided are a display device and a method of manufacturing the same. A display device includes a coplanar thin-film transistor and a capacitor. The coplanar thin-film transistor comprises a gate electrode, an active layer including an oxide semiconductor, a source electrode and a drain electrode. The capacitor comprises a lower electrode, intermediate electrode and upper electrode. And the lower electrode is comprised of the same material as the active layer, and is conductivized. Also, the upper electrode is connected to the lower electrode. By using the conductivized lower electrode, the capacitor is configured to operate as multiple capacitors. Thus, the size of the capacitor is reduced, and sufficient capacitance may be secured with the capacitor with a smaller area. In this way, the area of each sub-pixel in the display device may be reduced, thereby achieving high resolution.

Abstract: A FET type gas-sensitive device has a floating electrode formed in a horizontal direction. The device achieves noise reduction, process simplification, pollution control, sensing speed improvement, various sensing material applicability and mechanical stability etc. in comparison with a gas-sensitive device that is vertically stacked with a floating electrode, a sensing material layer and a control electrode. The device can be assembled easily with a plurality of gas-sensitive devices being operated by various sensing mechanisms in one substrate.

Abstract: An OLED display and a method of manufacturing thereof are disclosed. In one aspect, the display includes a scan line formed over a substrate and configured to transfer a scan signal, a data line and a driving voltage line crossing the scan line and respectively configured to transfer a data voltage and a driving voltage, and a switching transistor electrically connected to the scan line and the data line and including a switching drain electrode configured to output the data voltage. The display also includes a driving transistor including a driving gate electrode, a driving drain electrode, and a driving source electrode electrically connected to the switching drain electrode. The display further includes a storage capacitor including a first storage electrode electrically connected to the driving gate electrode and a second storage electrode formed on the same layer as the driving voltage line.

Abstract: A lighting may include a substrate, a light emitting device disposed on the substrate, a wavelength conversion layer which is disposed on the light emitting device and converts a part of first light emitted from the light emitting device into second light having a wavelength different from that of the first light, and a resin which is disposed on the substrate and buries the light emitting device and at least a portion of the wavelength conversion layer. An area of the top surface of the wavelength conversion layer is greater than that of the bottom surface of the wavelength conversion layer. The side surface of the wavelength conversion layer is inclined at a predetermined angle with respect to the top surface or the bottom surface.

Abstract: An organic light emitting diode display comprises a substrate comprising a major surface; first, second, third and fourth electrodes positioned over the substrate; a pixel defining layer positioned over the plurality of electrodes and comprising first, second, third and fourth openings; and a spacer positioned over the pixel defining layer. The first, second, third and fourth openings overlap the first, second, third and fourth electrodes, respectively, when viewed in a viewing direction perpendicular to the major surface. The first, second, third and fourth openings comprise first, second, third and fourth corners, respectively, wherein the first, second, third and fourth corners neighbor one another when viewed in the viewing direction. When viewed in the viewing direction, the spacer comprises at least a portion placed within an imaginary polygon defined by the first, second, third and fourth corners.

Abstract: A semiconductor device—e.g., a super junction power MOSFET—includes a number of columns of one type of dopant formed in a region of another type of dopant. Generally speaking, the columns are modulated in some manner. For example, the widths (e.g., diameters) of some columns are greater than the widths of other columns.

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes power rails that provide power to the transistors. The power rails extend in a second direction orthogonal to the first direction. The device further includes M1 layer interconnects extending between the power rails. At least one of the M1 layer interconnects is coupled to at least one of the transistors. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only.

Abstract: A substrate structure including a carrier and a substrate is provided. The carrier includes a release layer, a dielectric layer and a metal layer. The dielectric layer is disposed between the release layer and the metal layer. The substrate includes a packaging region and a peripheral region. The peripheral region is connected to the packaging region and surrounds the packaging region. The peripheral region or the packaging region has a plurality of through holes. The substrate is disposed on the carrier. The release layer is located between the substrate and the dielectric layer. The release layer and the dielectric layer are filled in the through hole such that the substrate is separably attached to the carrier.

Abstract: Disclosed herein is an OLED light emitting device and the production method thereof and a display apparatus. The OLED light emitting device includes a base substrate, and an anode, a cathode, and a light emitting layer located between the anode and the cathode, which are provided on the base substrate, and the OLED light emitting device further comprises a dissociation layer for dissociating excitons which arrive at the dissociation layer into holes and electrons; wherein the dissociation layer is provided between the light emitting layer and the anode in the case where the electron mobility is greater than the hole mobility; and the dissociation layer is provided between the light emitting layer and the cathode in the case where the hole mobility is greater than the electron mobility.

Abstract: A semiconductor device includes: a substrate including a channel region; a gate dielectric a tunneling layer, a charge storage layer, and a blocking layer sequentially disposed on the channel region; and a gate electrode disposed on the gate dielectric, wherein the tunneling layer has variations in nitrogen concentrations in a direction perpendicular to the channel region, and has a maximum nitrogen concentration in a position shifted from a center of the tunneling layer toward the charge storage layer.

Abstract: An integrated waveguide structure with perforated chip edge seal and methods of manufacture are disclosed herein. The structure includes a guard ring structure surrounding an active region of an integrated circuit chip. The structure further includes a gap in the guard ring structure which is located at a predetermined level of the integrated circuit chip. The structure further includes a waveguide structure formed on a substrate of the integrated circuit chip. The structure further includes a fiber optic optically coupled to the waveguide structure through the gap formed in the guard ring structure.

Abstract: A method for fabricating metal interconnect structure is disclosed. The method includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the metal interconnection; and using the spacer as mask to remove part of the first IMD layer for forming an opening in the first IMD layer.

Abstract: Fabricating an optics wafer includes providing a wafer comprising a core region composed of a glass-reinforced epoxy, the wafer further comprising a first resin layer on a top surface of the core region and a second resin layer on a bottom surface of the core region. The wafer further includes vertical transparent regions that's extend through the core region and the first and second resin layers. The wafer is thinned from its top surface and its bottom surface so that a resulting thickness is within a predetermined range without causing glass fibers of the core region to become exposed. Optical structures ate provided on one or more exposed surfaces of at least some of the transparent regions.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.

Abstract: A method of inspecting and forming sapphire structures. The method of inspecting a sapphire structure may include providing an annealed sapphire structure, and measuring a profile of at least a portion of the annealed sapphire structure. The profile of at least the portion of the annealed sapphire structure may be measured using a non-x-ray based measuring device. Additionally, the method of inspecting may include identifying a defect within at least a portion of the measured profile of the annealed sapphire structure.

Abstract: A display unit including a first substrate and a second substrate that are disposed to face each other, a first organic insulating layer on the first substrate, a plurality of light-emitting elements arrayed in a display region, the display region on the first organic insulating layer and facing the second substrate and a first moisture-proof film covering the first organic insulating layer in a peripheral region, in which the peripheral region is provided on the first substrate and surrounds the display region.

Abstract: Diode includes first metal layer, coupled to p-type III-N layer and to first terminal, has a substantially equal lateral size to the p-type III-N layer. Central portion of light emitting region on first side and first metal layer includes first via that is etched through p-type portion, light emitting region and first part of n-type III-N portion. Second side of central portion of light emitting region that is opposite to first side includes second via connected to first via. Second via is etched through second part of n-type portion. First via includes second metal layer coupled to intersection between first and second vias. Electrically-insulating layer is coupled to first metal layer, first via, and second metal layer. First terminals are exposed from electrically-insulating layer. Third metal layer including second terminal is coupled to n-type portion on second side of light emitting region and to second metal layer through second via.