Abstract: Methods for fabricating a graphene nanoribbon array in accordance with several embodiments of the present invention can include the steps of depositing PMMA dots on a substrate in an m×n grid, to selectively seed graphene flakes on the substrate by controlling the growth of the graphene flakes on the substrate during the graphene deposition. The methods can further include the steps of masking the graphene flake edges with an insulator layer, at a very low deposition time or at a lower precursor concentration, to ensure there are not enough insulator molecules to form a complete layer over the flakes, but only enough insulator to form around the flakes edges. Once the graphene flake edges are masked, the bulk graphene can be etched, and the masking insulator can be removed to expose the resulting graphene nanoribbon.

Abstract: An image sensor may include: a trench formed in a substrate; an impurity region formed in the substrate to be in contact with the trench; and a re-crystallization layer formed in the substrate to be in contact with bottom and side surfaces of the trench and a surface of the substrate. The re-crystallization layer may contain one or more kinds of elements different from an element constituting the substrate.

Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.

Abstract: A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer.

Abstract: Methods of forming the same include forming a stack of layers of alternating materials, including first layers of sacrificial material and second layers of channel material. The first layers are recessed relative to the second layers with an etch that etches the second layers at a slower rate than the first layers to taper ends of the second layers. First spacers are formed in recesses formed by recessing the first layers. Second spacers are formed in recesses formed by recessing the first layers. The first spacers are etched to expose sidewalls of the second spacer. Source/drain extensions are formed in contact with exposed ends of the second layers.

Abstract: An organic light emitting diode display device includes: a substrate; a scan line configured to transfer a scan signal; a data line and a driving voltage line configured to transfer a data voltage and a driving voltage, respectively; a switching transistor including a switching drain electrode configured to output the data voltage; a driving transistor including a driving gate electrode connected with the switching drain electrode; a storage capacitor including a first storage electrode connected with the driving gate electrode and a second storage electrode connected with the driving voltage line; and an organic light emitting diode connected with a driving drain electrode of the driving transistor. The storage capacitor includes: a connector in which an edge of the second storage electrode is offset from an edge of the first storage electrode in a direction toward the center of the second storage electrode, and a storage compensator facing the connector.

Abstract: A technique relates to a trilayer Josephson junction structure. A dielectric layer is on a base electrode layer that is on a substrate. A counter electrode layer is on the dielectric layer. First and second counter electrodes are formed from the counter electrode layer. First and second dielectric layers are formed from the dielectric layer. First and second base electrodes are formed from base electrode layer. The first counter electrode, first dielectric layer, and first base electrode form a first stack. The second counter electrode, second dielectric layer, and second base electrode form a second stack. A shunting capacitor is between first and second base electrodes. An ILD layer is deposited on the substrate, the first and second counter electrodes, and the first and second base electrodes. A contact bridge connects the first and second counter electrodes. An air gap is formed underneath the contact bridge by removing ILD.

Abstract: This invention discloses a light emitting element to solve the problem of lattice mismatch and inequality of electron holes and electrons of the conventional light emitting elements. The light emitting element comprises a gallium nitride layer, a gallium nitride pyramid, an insulating layer, a first electrode and a second electrode. The gallium nitride pyramid contacts with the gallium nitride layer, with a c-axis of the gallium nitride layer opposite in direction to a c-axis of the gallium nitride pyramid, and with an M-plane of the gallium nitride layer parallel to an M-plane of the gallium nitride pyramid, with broken bonds at the mounting face of the gallium nitride layer and the larger end face of the gallium nitride pyramid welded with each other, with the gallium nitride layer and the gallium nitride pyramid being used as a p-type semiconductor and an n-type semiconductor respectively.

Abstract: A lighting device and a method for producing a lighting device are disclosed. In an embodiment, the lighting device includes a carrier, at least one optoelectronic illuminant arranged on the carrier, the illuminant configured to emit light into an emission area and a color scattering layer located in the emission area, the color scattering layer configured to generate a color by scattering of light at a surface of the color scattering layer facing away from the illuminant.

Abstract: The low reflective display device a low reflective unit including a plurality of optical lens structures arranged in a position-corresponding manner to the plurality of sub-pixels thereon respectively; a light-reflective layer covering the side-wall face of each optical lens structure; and a light-absorbing member arranged to fill spaces between neighboring optical lens structures, wherein the bottom face of each of the plurality of optical lens structures completely covers the top face of the corresponding sub-pixel among the plurality of sub-pixels, wherein the bottom face of each of the plurality of optical lens structures receives all of light-beams generated from the corresponding sub-pixel, and wherein the bottom face of each of the plurality of optical lens structures has an area that is greater than or equal to a top face area of the corresponding sub-pixel.

Abstract: A third dummy trench (11) is orthogonal to the first and second dummy trenches (9,10) in the dummy cell region of a substrate end portion. An interlayer insulating film (13) insulates the p-type diffusion layer (3,4) in the dummy cell region of a substrate center portion situated between the first and second dummy trenches (9,10) from the emitter electrode (14). The third dummy trench (11) separates the p-type diffusion layer (3,4) in the dummy cell region of the substrate center portion from the p-type diffusion layer (3,4,15) in the dummy cell region of the substrate end portion connected to the emitter electrode (14). A p-type well layer (15) is provided deeper than the third dummy trench (11) in the substrate end portion. The third dummy trench (11) is provided closer to a center of the n-type substrate than the p-type well layer (15).

Abstract: A packaging substrate includes a core layer having a first surface and a second surface. A group of ground pads is disposed on the second surface within a central region. A group of first power pads is disposed on the second surface within the central region. A plurality of signal pads is disposed on the second surface within a peripheral region that encircles the central region on the second surface. A first block-type via is embedded in the core layer within the central region. The group of ground pads is electrically connected to the first block-type via. A second block-type via is embedded in the core layer within the central region. The group of first power pads is electrically connected to the second block-type via.

Abstract: A display unit including a first substrate and a second substrate that are disposed to face each other, a first organic insulating layer on the first substrate, a plurality of light-emitting elements arrayed in a display region, the display region on the first organic insulating layer and facing the second substrate and a first moisture-proof film covering the first organic insulating layer in a peripheral region, in which the peripheral region is provided on the first substrate and surrounds the display region.

Abstract: Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.

Abstract: A transparent light emitting diode film is disclosed. The transparent light emitting diode film includes a base, an electrode layer positioned on the base and having at least one pattern, a pad formed on at least a portion of the electrode layer, a light emitting diode positioned on the pad, and an adhesive layer formed on at least another portion of the electrode layer. The adhesive layer includes first and second adhesive layers each having a different adhesive strength.

Abstract: A display device is disclosed including an array substrate including a plurality of pixels arranged in a display region, the display region including a planar region and a curved region, and a sealing layer covering the plurality of pixels and arranged across the display region, wherein the sealing layer includes a first organic insulation layer and a second organic insulation layer, a film thickness of the first organic insulation layer is more than a film thickness of the second organic insulation layer in the planar region, a film thickness of the second organic insulation layer is more than a film thickness of the first organic insulation layer in the curved region, and a hardness of the second organic insulation layer is lower than a hardness of the first organic insulation layer.

Abstract: A chip package is disclosed that includes an electronic chip having a plurality of die pads formed on a top surface thereof, with a polyimide flex layer positioned thereon by way of an adhesive layer. A plurality of vias is formed through the polyimide flex layer and the adhesive layer corresponding to the die pads. A plurality of metal interconnects are formed on the polyimide flex layer each having a cover pad covering a portion of a top surface of the polyimide flex layer, a sidewall extending down from the cover pad and through the via along a perimeter thereof, and a base connected to the sidewall and forming an electrical connection with a respective die pad. Each of the base and the sidewall is formed to have a thickness that is equal to or greater than a thickness of the adhesive layer.

Abstract: Disclosed herein is an apparatus for processing a substrate that forms a hole in a substrate while reducing a burr in the hole so that a module device can be inserted into the hole to reduce the thickness of a display device, and the display device using the apparatus. The apparatus for processing the substrate comprises a body configured to operably be rotatable, and a cylindrical cutting tip at an end of the body. The bottom surface of the cutting tip is in an acute angle with respect to a contact surface of the substrate to allow formation of a groove at the substrate.

Abstract: CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.

Abstract: A transistor including a substrate, a gate layer, a first insulating layer, an active layer, a source and a drain is provided. The gate layer is disposed on the first insulating layer, and has a plurality of first through holes. The first insulating layer covers the gate layer and a part of the substrate exposed by the first through holes, and forms a plurality of recesses respectively corresponding to the first through holes. The active layer is disposed on the first insulating layer, and has a plurality of second through holes. The second through holes communicate with the recesses, respectively. The source is disposed on a part of the active layer. The drain is disposed on another part of the active layer. A manufacturing method of the transistor is also provided.