Abstract: Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.

Abstract: A chip package including a first substrate is provided. The first substrate includes a sensing device. A second substrate is attached onto the first substrate and includes an integrated circuit device. A first conductive structure is electrically connected to the sensing device and the integrated circuit device through a redistribution layer disposed on the first substrate. An insulating layer covers the first substrate, the second substrate and the redistribution layer. The insulating layer has a hole therein and a second conductive structure is disposed under the bottom of the hole. A method for forming the chip package is also provided.

Abstract: An imaging device includes a semiconductor substrate and at least one unit pixel cell provided to a surface of the semiconductor substrate. Each of the at least one unit pixel cell includes: a photoelectric converter including a pixel electrode and a photoelectric conversion layer located on the pixel electrode, the photoelectric converter converting incident light into electric charges; a charge detection transistor that includes a part of the semiconductor substrate and detects the electric charges; and a reset transistor that includes a gate electrode and initializes a voltage of the photoelectric converter. The pixel electrode is located above the charge detection transistor. The reset transistor is located between the charge detection transistor and the pixel electrode. When viewed from a direction normal to the surface of the semiconductor substrate, at least a part of the gate electrode is located outside the pixel electrode.

Abstract: A flexible display device comprises a flexible substrate including a display area and a non-display area; a display layer in the display area on a first surface of the flexible substrate; a polarizing plate on the display layer; and a cover coat in the non-display area on the first surface of the flexible substrate, the cover coat including a first end portion overlapping with the polarizing plate. At least a portion of the non-display area of the flexible substrate and the cover coat are bendable in a bending direction.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure over a semiconductor substrate. The semiconductor device structure also includes a second fin structure over the semiconductor substrate. The second fin structure has a lower height than that of the first fin structure. The second fin structure includes a first sidewall and a second sidewall, and the first sidewall and the second sidewall surround a recess over the second fin structure.

Abstract: A method involving a barrier for preventing eutectic break-through in through-substrate vias is disclosed. The method generally includes steps (A) to (D). Step (A) may form one or more vias through a substrate. The substrate generally comprises a semiconductor. Step (B) may form a first metal layer. Step (C) may form a barrier layer. The barrier layer generally resides between the vias and the first metal layer. Step (D) may form a second metal layer. The second metal layer may be in electrical contact with the first metal layer through the vias and the barrier layer.

Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/?10%) and less than or equal to 60 Angstroms (+/?10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/?10%) or 30-50 atomic percent (+/?10%).

Abstract: High integrity, lower power consuming semiconductor devices and methods for manufacturing the same. The semiconductor device includes: semiconductor substrate; a well region in the semiconductor substrate; an interlayer structure over the well region, the interlayer structure including a back gate conductor, semiconductor fins at both sides of the back gate conductor and respective back gate dielectric isolating the back gate conductor from the semiconductor fins, respectively, wherein the well region functions as one portion of a conductive path of the back gate conductor; a punch-through stop layer at a lower portion of the semiconductor fin; a front gate stack intersecting the semiconductor fin, the front gate stack including a front gate dielectric and a front gate conductor and the front gate dielectric isolating the front gate conductor from the semiconductor fin; and a source region and a drain region connected to a channel region provided by the semiconductor fin.

Abstract: A flexible display device includes a base substrate defining a display area and a non-display area; a thin film transistor in the display area of the base substrate; an organic light emitting diode on and connected with the thin film transistor; an encapsulation layer on the organic light emitting diode; and a crack preventing portion in the non-display area defined by the base substrate.

Abstract: Techniques are disclosed for making a flexible laminated circuit board using a metal conductor onto which a SMD may be attached. Conductive metal strips may be laminated to form a flexible substrate and the metal strips may then be perforated for the placement of LED package leads. The LED packages may be attached to the conductive strips using solder or a conductive epoxy and the upper laminate layer may include perforations exposing portions of the metal strips for the attachment of the LED packages. Alternatively, strings of LED packages may be fabricated by attaching LED packages to conductive strips and these strings may be laminated between flexible sheets to form a laminated LED circuit. Plastic housings may aid in attaching the LED packages to the conductive strips. The plastic housings and/or the laminate sheets may be made of a reflective material.

Abstract: A magnetic junction and method for providing the magnetic junction are described. The method includes providing a free layer, providing a pinned layer and providing a nonmagnetic spacer between the free and pinned layers. The free layer is switchable between stable magnetic states using a write current passed through the magnetic junction. At least one of the step of providing the free layer and the step of providing the pinned layer includes depositing a magnetic layer; depositing an adsorber layer on the magnetic layer and performing at least one anneal. The magnetic layer is amorphous as-deposited and includes an interstitial glass-promoting component. The adsorber layer attracts the interstitial glass-promoting component and has a lattice mismatch with the nonmagnetic spacer layer of not more than ten percent. Each of the anneal(s) is at a temperature greater than 300 degrees Celsius and not more than 425 degrees Celsius.

Abstract: The present invention discloses a display panel, which includes a display unit. The display unit includes an anode layer, a hole injection layer, a hole transport layer, a luminescent material layer, an electron transporting layer, an electron injection layer, a cathode layer. The luminescent material layer includes the first luminescent material block, the second luminescent material block, and the third luminescent material block. The first luminous material block and the second luminous material block are partially overlapped, and the second luminous material block and the third luminescent material block are partially overlapped. The present invention is beneficial to producing a pixel having a smaller dimension in the display panel.

Abstract: An OLED apparatus that may include a reflection-anode, a transparent-cathode, and a plurality of stacks between the reflection-anode and the transparent-cathode, wherein, among the plurality of stacks, a thickness of the stack disposed relatively close to the transparent-cathode is larger than a thickness of the stack disposed relatively close to the reflection-anode so that it is possible to optimize a micro-cavity of light emitted from the plurality of stacks, thereby improving a light-emission efficiency and a color reproduction ratio and reducing a color change rate in accordance with a viewing angle.

Abstract: An organic light-emitting display apparatus includes a first substrate corresponding to a display area and a periphery area, a second substrate facing the first substrate, a first metal layer at the periphery area of the first substrate, and defining a plurality of first holes, a second metal layer on the first metal layer, and defining a plurality of second holes that are differently sized than the first holes, a third metal layer on the second metal layer, and defining a plurality of third holes that are differently sized than the second holes, and a sealing member bonding the first substrate and the second substrate, and filling a partial region of the first, second, and third holes.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body which is provided on a substrate and in which an insulating film and an electrode film are alternately stacked. The semiconductor memory device also includes an insulating member which penetrates the stacked body in a stacking direction of the insulating film and the electrode film to thereby separate the stacked body. The semiconductor memory device also includes a semiconductor pillar which penetrates the stacked body in the stacking direction. A maximum portion of the insulating member where a first distance from a side surface of the insulating member to a central plane of the insulating member becomes maximum and a maximum portion of the semiconductor pillar where a second distance from a side surface of the semiconductor pillar to a center line of the semiconductor pillar becomes maximum being provided in different positions in the stacking direction.

Abstract: Embodiments of the present disclosure provide a manufacturing method for a flexible device and a flexible display device. The manufacturing method for a flexible device comprises: step S1, forming an organosiloxane layer on a supporting substrate; step S2, forming a flexible substrate on the organosiloxane layer; step S3, forming a display device on the flexible substrate; step S4, performing an oxidation treatment on a surface of the organosiloxane layer that contacts the supporting substrate such that a silicon dioxide layer is formed between the organosiloxane layer and the supporting substrate; and step S5, peeling off the supporting substrate from the silicon dioxide layer.

Abstract: A power semiconductor device has a metal molded body forming a first connecting conductor. From a first main surface of the metal molded body there is a first recess having a first base in which a first power semiconductor component is arranged which faces the first base and is connected in an electrically conductive manner. From a second main surface of the metal molded body, a second recess has a second base, and a second power semiconductor component is arranged with the first contact surface thereof associated with the second base connected in an electrically conductive manner to this base. An insulating material layer is on both main surfaces, filling and completely covering the recess, wherein the first insulating layer has an electrically conductive first via which connects a second contact surface of the first power semiconductor component in an electrically conductive manner to a first conducting surface arranged on the first insulating layer.

Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating, wherein the semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material, and an anisotropic nanocrystalline shell composed of a second, different, semiconductor material surrounding the anisotropic nanocrystalline core. The anisotropic nanocrystalline core and the anisotropic nanocrystalline shell form a quantum dot. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core.

Abstract: A light emitting device of the invention includes a substrate; a light emitting element mounted on the upper surface of the substrate; a wire that is electrically connected to the light emitting element; and a plate-shaped light-transmissive member that covers the light emitting element. The wire has a stack structure in which a first bonding ball, a bonding wire, and a second bonding ball are stacked in that order, the stack structure is disposed on the upper surface of the light emitting element, and the plate-shaped light-transmissive member is disposed above the stack structure.

Abstract: The present invention makes it possible, in a manufacturing process of a semiconductor device, to inhibit: impurities from diffusing from a substrate to a semiconductor layer; and the withstand voltage of a transistor from deteriorating. In the present invention, a first electrically conductive type epitaxial layer is formed over a first electrically conductive type base substrate. The impurity concentration of the epitaxial layer is lower than that of the base substrate. A second electrically conductive type first embedded layer and a second electrically conductive type second embedded layer are formed in the epitaxial layer. The second embedded layer is deeper than the first embedded layer, is kept away from the first embedded layer, and has an impurity concentration lower than the first embedded layer. A transistor is further formed in the epitaxial layer.