Patents Examined by Thomas J. Hiltunen
  • Patent number: 10848141
    Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: November 24, 2020
    Assignee: pSemi Corporation
    Inventors: Payman Shanjani, Eric S. Shapiro
  • Patent number: 10848140
    Abstract: System and method for detecting clock failure are disclosed. The system includes a pulse train generator, a delay circuit, and a failure detection circuit. The pulse train generator receives an input clock and generates a pulse train including a plurality of pulses aligned with a set of rising edges and a set of falling edges of the input clock. The delay circuit delays the input clock by a first time-interval to generate a first delayed clock. The failure detection circuit receives the pulse train and the first delayed clock from the pulse train generator and the delay circuit, respectively, and generates a clock detection signal that transitions from a first logic state to a second logic state based on a failure in the input clock.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: November 24, 2020
    Assignee: NXP USA, INC.
    Inventors: Dinesh Joshi, Nidhi Sinha, Akshay Kumar Pathak
  • Patent number: 10848052
    Abstract: The present invention concerns a method for controlling the temperature of a multi-die power module, comprising: determining and memorizing a first weighted arithmetic mean of junction temperatures of the dies of the multi-die power module, determining successively another weighted arithmetic mean of junction temperatures of the dies, checking if the difference between the other weighted arithmetic mean and the memorized weighted arithmetic mean is lower than a first predetermined value, enabling a modification of the duty cycle of an input signal to apply to at least one selected die of the multi-die power module if the difference is lower than a first predetermined value, disabling a modification of the duty cycle of the input signal to apply to the at least one die of the multi-die power module if the difference is not lower than the first predetermined value.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: November 24, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Jeffrey Ewanchuk, Julio Cezar Brandelero, Stefan Mollov, Jonathan Robinson
  • Patent number: 10847977
    Abstract: A method is provided for power limiting in a power inverter configured to produce an output voltage and having a voltage regulator with a voltage setpoint defined for no load on an external bus line. The method includes determining a power level related to a load on the external bus line, determining an adjusted voltage setpoint based on the power level, including: decreasing the voltage setpoint to the adjusted voltage setpoint having a first value when the power level is above a maximum threshold, increasing the voltage setpoint to the adjusted voltage setpoint having a second value when the power level is below a minimum threshold, and slewing the adjusted voltage setpoint to the voltage setpoint so that the adjusted voltage setpoint has a third value when the power level is within a range defined by the maximum threshold and the minimum threshold.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: November 24, 2020
    Assignee: Nexus Technologies, Inc.
    Inventor: Belvin Freeman
  • Patent number: 10840896
    Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: November 17, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwan Yeob Chae, Jong-Ryun Choi
  • Patent number: 10838442
    Abstract: A semiconductor device including an input terminal to which a power source, for which the time until a voltage equal or greater than a predetermined voltage value is output fluctuates according to an external environment, is connected, a power source section to which the input terminal supplies power from the power source, a power source supply terminal that supplies power to a driven semiconductor device, a switch that controls a connection between the power source section and the power source supply terminal, and a voltage regulator to which the input terminal supplies power from the power source, and that supplies a voltage to the power source supply terminal is provided.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: November 17, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Shigeru Nagatomo
  • Patent number: 10840895
    Abstract: According to one or more embodiments of the present invention, a delay circuit includes a first sub-circuit that delays a leading edge of an input signal according to first control settings, the input signal being for an electric device. The delay circuit further includes a second sub-circuit that delays a trailing edge of the input signal according to second control settings. An output signal from the delay circuit is received by the electric device.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul Alan Bunce, John Davis, Brian James Yavoich, Russell Hayes
  • Patent number: 10833653
    Abstract: Aspects of the invention include a circuit including a power circuit having an amplifier, a resistor, a current source, and a first node, one end of the resistor being configured to couple to a power supply, the first node being coupled to an opposite end of the resistor, a first input terminal of the amplifier, and the current source. A voltage sensitive circuit includes a logic gate coupled to both a second input terminal of the amplifier and an output terminal of the amplifier at a second node.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Sperling, Akil Khamisi Sutton, Pawel Owczarczyk, Erik English
  • Patent number: 10833574
    Abstract: A switching element control device for controlling a switching element incorporating a reverse conducting diode is provided. The switching element control device includes: a voltage detection circuit detecting a voltage across first and second main electrodes of the switching element; a comparator circuit comparing the voltage detected by the voltage detection circuit with a threshold voltage; and a drive circuit controlling driving of the switching element. The comparator circuit controls the drive circuit so that an on signal is not provided to the switching element when the detected voltage exceeds the threshold voltage.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: November 10, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Mitsuru Kaneda, Tetsuo Takahashi, Shinya Soneda, Ryu Kamibaba
  • Patent number: 10833652
    Abstract: Systems, computer-implemented methods, and computer program products that can facilitate superconducting resonator definition based on one or more superconducting circuit attributes, are described. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a resonant circuit component that derives a resonant circuit indicative of a superconducting resonator of a superconducting circuit based on one or more attributes of the superconducting circuit. The computer executable components can further comprise a resonator definition component that defines a frequency value of the superconducting resonator based on the resonant circuit.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Salvatore Bernardo Olivadese
  • Patent number: 10830799
    Abstract: A power MOSFET Rdson compensation device comprising analog circuitry receives an input signal proportional to a voltage drop across a power MOSFET, one or more base reference voltages, a voltage-dependent reference voltage, and a temperature-dependent reference voltage. The analog circuitry is configured to produce an output current corresponding to the input signal with compensation for voltage and temperature variation of a drain-source on resistance of the power MOSFET.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: November 10, 2020
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventor: Gilbert S. Z. Lee
  • Patent number: 10833672
    Abstract: A driving circuit for an N-channel or NPN-type high-side transistor includes: a level shift circuit configured to level-shift an input signal; and a buffer configured to drive the N-channel or NPN-type high-side transistor according to an output of the level shift circuit, wherein the level shift circuit includes: a differential conversion circuit of an open drain type configured to convert the input signal into a differential signal; a latch circuit configured to perform a state transition with a differential output of the differential conversion circuit as a trigger; and an assist circuit configured to inject an assist current into the latch circuit in synchronization with the input signal.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: November 10, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Hiroki Niikura
  • Patent number: 10826388
    Abstract: A charge pump circuit includes a voltage output terminal, a flying capacitor, and a current source. The flying capacitor includes a first terminal coupled to the voltage output terminal, and a second terminal coupled to an output terminal of a drive circuit. The current source includes a first terminal coupled to the voltage output terminal, and a second terminal coupled to a power supply rail.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: November 3, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Maciej Piotr Jankowski
  • Patent number: 10826480
    Abstract: An integrated circuit includes a gate driver circuit that controls high side and low side transistors to operate in buck or boost mode. In buck operating mode, after switching off the low side transistor, the gate driver circuit controls the high side transistor in a constant current mode. After the low side transistor is disabled and no longer conducts current, then the gate driver circuit controls the high side transistor to operate in full-enhancement mode. In boost operating mode, after switching off the high side transistor, the gate driver circuit controls the low side transistor in a constant current mode. After the high side transistor is disabled, then the gate driver circuit controls the low side switching transistor to operate in full-enhancement mode. In both buck and boost operation, the gate driver circuit operates without dead time in which both the high side and low side transistors are off.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: November 3, 2020
    Assignee: Active-Semi, Inc.
    Inventors: Thinh Ba Nguyen, Thien Khanh Luong, Thuc Huu Lam, Hue Khac Trinh
  • Patent number: 10819163
    Abstract: The present invention provides wireless power transmitting method and apparatus. The wireless power transmitting method according to an embodiment of the present invention may measure a resonance frequency while changing an operating frequency of a resonance circuit, compare the measured resonance frequency with a reference frequency, and wirelessly transmit power when the measured resonance frequency is lower than the reference frequency. The reference frequency may be determined based on two or more among a self resonance frequency of the resonance circuit, a first resonance frequency measured for a receiving device, a second resonance frequency measured for a reference object and a third resonance frequency measured for the receiving device and the reference object.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: October 27, 2020
    Assignee: HITACHI-LG DATA STORAGE KOREA, INC.
    Inventors: Cheol Jin, Hogil Lee
  • Patent number: 10802516
    Abstract: Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit board that regulates a first voltage; a semiconductor device on the circuit board that receives the first voltage through a power line in the circuit board. The semiconductor device includes: a substrate on the circuit board, stacked via conductive balls, that receives the first voltage from the power line via the conductive balls; a plurality of dies on the semiconductor device, stacked via bumps, each die including, a first conductive via that receives the first voltage via the bumps; a plurality of pillars between adjacent dies and couple the first conductive vias of the adjacent dies; and a sense node switch circuit that selectively couples one first conductive via of one die among the plurality of dies to the regulator.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: October 13, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Adam S. El-Mansouri, Fuad Badrieh, Brent Keeth
  • Patent number: 10797692
    Abstract: An integrated circuit device includes a circuit device main body which is configured to execute a predetermined processing function, a communication control circuit which is configured to perform data communication with an external control device and an operation mode determination unit which is configured to selectively determine a normal mode for executing the processing function or a debug mode for setting an execution condition of the processing function as an operation mode of the circuit device main body. The operation mode determination circuit is configured to operate in accordance with an internal clock and to generate an operation mode output value for determining the operation mode of the circuit device main body according to a logical state of a particular one communication signal which is data-communicated with the external control device after a reset operation performed by a reset circuit is released.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 6, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masashi Akahane
  • Patent number: 10797683
    Abstract: A calibration circuit, including a duty cycle correction circuit and a phase correction circuit and associated calibrating method, are provided. Firstly, a first duty cycle adjusted clock and a second duty cycle adjusted clock are generated by the duty cycle correction circuit based on a first input clock and a second input clock, respectively. Then, a first delay adjusted clock and a second delay adjusted clock are generated by the phase correction circuit based on a phase of the first duty cycle adjusted clock, and a detection signal is generated. The detection signal is related to a duty cycle of the first input clock, a duty cycle of the second input clock, and a phase difference between the second delay adjusted clock and the first delay adjusted clock. Later, the duty cycle correction circuit and the phase correction circuit are controlled in response to the detection signal.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 6, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Vinod Kumar Jain, Chi-Yeu Chao, Prateek Kumar Goyal, Han-Kyul Lim
  • Patent number: 10790812
    Abstract: An integrated circuit includes a gate driver circuit that controls high side and low side transistors to operate in buck or boost mode. In buck operating mode, after switching off the low side transistor, the gate driver circuit controls the high side transistor in a constant current mode. After the low side transistor is disabled and no longer conducts current, then the gate driver circuit controls the high side transistor to operate in full-enhancement mode. In boost operating mode, after switching off the high side transistor, the gate driver circuit controls the low side transistor in a constant current mode. After the high side transistor is disabled, then the gate driver circuit controls the low side switching transistor to operate in full-enhancement mode. In both buck and boost operation, the gate driver circuit operates without dead time in which both the high side and low side transistors are off.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: September 29, 2020
    Assignee: Active-Semi, Inc.
    Inventors: Thinh Ba Nguyen, Thien Khanh Luong, Thuc Huu Lam, Hue Khac Trinh
  • Patent number: 10790741
    Abstract: In a power converter that includes a switched-capacitor circuit connected to a switched-inductor circuit, reconfiguration logic causes the switched-capacitor circuit to transition between first and second switched-capacitor configurations with different voltage-transformation ratios. A compensator compensates for a change in the power converter's forward-transfer function that would otherwise result from the transition between the two switched-capacitor configurations.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: September 29, 2020
    Assignee: pSemi Corporation
    Inventor: Gregory Szczeszynski