Patents Examined by Thomas J. Hiltunen
  • Patent number: 11444626
    Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: September 13, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shailesh Ganapat Ghotgalkar, Wei Fu, Venkatseema Das, Jiankun Hu
  • Patent number: 11442485
    Abstract: An integrated circuit chip and test method thereof are provided. The integrated circuit chip of the disclosure includes a first chip circuit and a plurality of external pins. The first chip circuit includes a plurality of first internal pads, a plurality of second internal pads and a current mirror circuit. The current mirror circuit is coupled to one of the plurality of first internal pads and the plurality of second internal pads. The plurality of external pins are coupled to the plurality of first internal pads.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: September 13, 2022
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yi-Hsuan Cheng, Ying-Chung Tseng
  • Patent number: 11444614
    Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the abovementioned performance improvements are maintained.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: September 13, 2022
    Assignee: pSemi Corporation
    Inventors: Payman Shanjani, Eric S. Shapiro
  • Patent number: 11442517
    Abstract: The invention provides an on-chip passive power supply compensation circuit, and an operational unit, a chip, a hash board and a computing device using the same. The on-chip passive power supply compensation circuit comprises: two or more to-be-powered voltage domains, wherein the to-be-powered voltage domains are connected in series between a power supply and ground; and two or more isolation regions, wherein the to-be-powered voltage domains are formed in the isolation regions, and the isolation regions are configured for isolating the to-be-powered voltage domains; the isolation regions are connected in series between the power supply and the ground, wherein the on-chip passive power supply compensation circuit further comprises power supply compensation units connected between the to-be-powered voltage domains and the isolation regions for providing power supply compensation to the to-be-powered voltage domains.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: September 13, 2022
    Assignee: CANAAN CREATIVE CO., LTD.
    Inventors: Jieyao Liu, Nangeng Zhang, Jingjie Wu, Shenghou Ma
  • Patent number: 11437907
    Abstract: Disclosed herein is a charge pump architecture in which boosting capacitors of adjacent stages are connected only by NMOS type transistors and comprising a first stage receiving a first voltage and outputting an internal voltage; a second stage receiving the internal voltage and outputting a second voltage at an output terminal, and an auxiliary stage connected to the output terminal, the first stage and second stage including a first type of MOS transistors transferring the voltage from input node internal boosting nodes and being cross-coupled; a second type of MOS transistors with their gate biased by a third type of MOS transistors and fourth type of MOS transistors; the third type of MOS transistors connecting the gate of the second type of MOS transistors; and the fourth type of MOS transistors connecting the gate of the second type of MOS transistors.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: September 6, 2022
    Assignee: SK hynix Inc.
    Inventors: Onur Aker, Marco Passerini
  • Patent number: 11431324
    Abstract: A bandgap circuit is disclosed. The bandgap circuit includes a current source configured to generate, using a bias voltage, a first current and a second current, a first bipolar device configured to sink the first current, and a second bipolar device configured to sink the second current via a bias resistor. The bandgap circuit further includes an amplifier circuit configured to generate the bias voltage using a first voltage drop across the first bipolar device and a second voltage drop across the series combination of the bias resistor and the second bipolar device. A compensation circuit is also included, where the compensation circuit is configured to adjust, based on a value of the bias resistor, a base current of the second bipolar device.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: August 30, 2022
    Assignee: Apple Inc.
    Inventors: Craig P. Finlinson, Mazen S. Soliman
  • Patent number: 11429127
    Abstract: An LDO regulator includes an error amplifier, a power transistor, a monitoring circuit and/or an adaptive pole adjusting circuit (APAC). The error amplifier compares a reference voltage and a feedback voltage to generate a first error voltage based on the comparison. The power transistor including a gate coupled to an output terminal of the buffer, regulates an input voltage based on a second error voltage which is generated based on the first error voltage to provide an output voltage to an output node. The monitoring circuit, connected to the output terminal of the buffer in parallel with the power transistor, generates a control voltage associated with a load current. The APAC, connected between the output terminal of the error amplifier and the ground voltage, selectively connects an adjusting capacitor between the output terminal of the error amplifier and the ground voltage in response to the control voltage.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: August 30, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seongwon Joo, Jeongkyun Woo, Jeongyeol Bae
  • Patent number: 11431530
    Abstract: A circuit for a transmitter driver is disclosed. The transmitter driver circuit includes a main voltage-mode driver circuit configured to receive an input signal at the input port and to drive an output signal at the output port. The transmitter driver circuit also includes a secondary circuit connected to the input port and the output port in parallel with the main voltage-mode driver circuit. The secondary circuit includes: a secondary voltage-mode driver circuit; a current source connected to the secondary voltage-mode driver circuit and controllable to enable or disable a current boost to the output signal; and a switch connected to the secondary voltage-mode driver circuit and controllable to enable or disable the secondary voltage-mode driver circuit to drive the output signal in parallel with the main voltage-driver circuit.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: August 30, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Euhan Chong
  • Patent number: 11422617
    Abstract: A power system may include a plurality of voltage regulator phases each configured to generate an output voltage at its output from an input voltage, a switched capacitor power converter sharing its output with the outputs of the plurality of voltage regulator phases and configured to, when enabled, generate the output voltage at its output from the input voltage, and a power controller configured to selectively enable and disable the switched capacitor power converter based on electrical current requirements of the power system.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 23, 2022
    Assignee: Dell Products L.P.
    Inventors: Lei Wang, John J. Breen, Mehran Mirjafari, Guangyong Y. Zhu
  • Patent number: 11422581
    Abstract: Various implementations described herein are related to a device having header circuitry with first transistors that are configured to receive a supply voltage and provide a dynamically biased voltage. The device may include reference generation circuitry having multiple amplifiers that are configured to receive the supply voltage and provide reference voltages based on the supply voltage. The device may include bias generation circuitry having second transistors configured to track changes in the dynamically biased voltage and adjust the dynamically biased voltage by generating bias voltages based on the reference voltages and by applying the bias voltages to the header circuitry so as to adjust the dynamically biased voltage.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: August 23, 2022
    Assignee: Arm Limited
    Inventors: Ranabir Dey, Vijaya Kumar Vinukonda
  • Patent number: 11422168
    Abstract: An on-chip low-voltage current sensing circuit for measuring current in an integrated circuit (IC). In one embodiment, an IC formed on a substrate, which includes a plurality of subcircuits, and a plurality of sensing circuits coupled to the plurality of subcircuits, respectively. The plurality of sensing circuits are configured to generate a plurality of currents, respectively, that are proportional to a plurality of load currents, respectively, consumed by the plurality of subcircuits, respectively, during operation thereof. A circuit is coupled to the plurality of sensing circuits and configured to generate a signal based on an aggregate of the plurality of currents.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: August 23, 2022
    Assignee: NXP USA, Inc.
    Inventor: Felipe Ricardo Clayton
  • Patent number: 11424676
    Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: August 23, 2022
    Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Vikas Rana, Marco Pasotti, Fabio De Santis
  • Patent number: 11418184
    Abstract: A system may include a sensor configured to output a sensor signal indicative of a distance between the sensor and a mechanical member associated with the sensor, a measurement circuit communicatively coupled to the sensor and configured to determine a physical force interaction with the mechanical member based on the sensor signal, and a compensator configured to monitor the sensor signal and to apply a compensation factor to the sensor signal to compensate for changes to properties of the sensor based on at least one of changes in a distance between the sensor and the mechanical member and changes in a temperature associated with the sensor.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: August 16, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Matthew Beardsworth, Tejasvi Das, Siddharth Maru, Luke Lapointe
  • Patent number: 11418174
    Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: August 16, 2022
    Assignee: Apple Inc.
    Inventors: Greg M. Hess, Vivekanandan Venugopal, Victor Zyuban
  • Patent number: 11411535
    Abstract: A device is disclosed that includes an insulating layer, a first electrode, a second electrode, and a bottom electrode. The insulating layer is disposed on a first surface of a substrate. The first electrode and the second electrode are disposed on a first surface of the insulating layer. The first electrode receives an input signal, and the second electrode outputs, in response to the input signal, an output signal. The bottom electrode is disposed on a second surface, opposite to the first surface, of the substrate and receives an operating voltage to modify a frequency of the output signal.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: August 9, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo Hwu, Ting-Hao Hsu
  • Patent number: 11393325
    Abstract: The circuit is of a loop-mountable unit of a fire alarm system, and includes: an adjustable current source, arranged to adjust the current from the loop through the power control circuit based on a control signal; an inverting amplifier, arranged to provide the control signal to the adjustable current source in which the control signal is based on the loop voltage; and a damper having an input for connection to a loop and an output connected to the inverting input of the inverting amplifier such that the voltage at the output of the damper is smoothed with respect to the voltage at its input.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: July 19, 2022
    Assignee: TYCO FIRE & SECURITY GMBH
    Inventors: Steven Ian Bennett, Paul W. Cottrell
  • Patent number: 11385668
    Abstract: An offset compensation device includes a first bias module and a second bias module. The first bias module includes a plurality of first current control circuits and a plurality of second current control circuits coupled in parallel. Each of the first current control circuits generates a first reference current, and each of the second current control circuits generates a second reference current. The second bias module includes a plurality of third current control circuits and a plurality of fourth current control circuits coupled in parallel. Each of the third current control circuits generates a third reference current, and each of the fourth current control circuits generates a fourth reference current. The second reference current is greater than the first reference current, and the fourth reference current is greater than the third reference current.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: July 12, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ting-Yao Huang, Po-Chih Wang, Ka-Un Chan
  • Patent number: 11385666
    Abstract: Circuitry comprising: a capacitor; first circuitry; and second circuitry, wherein the circuitry is operable to couple the capacitor to the first circuitry when the first circuitry is active, and to couple the capacitor to the second circuitry when the first circuitry is inactive or is not actively using the capacitor.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: July 12, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Hamed Sadati, John A. Breslin, Sushanth Hegde, John L. Melanson
  • Patent number: 11380679
    Abstract: Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul Fischer, Walid Hafez, Nicholas McKubre
  • Patent number: 11381231
    Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: July 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwan Yeob Chae, Jong-Ryun Choi