Abstract: A power management circuit operable to adjust voltage within a defined interval(s) is provided. The power management circuit is configured to generate a time-variant voltage for amplifying an analog signal based on a target voltage. In embodiments disclosed herein, the power management circuit can be configured to generate a lower initial target voltage at a start of the defined interval(s), such as during a cyclic prefix (CP) of an orthogonal frequency division multiplexing (OFDM) symbol, and dynamically adjust the initial target voltage, if necessary, within the defined interval(s) based on a time-variant power envelope of the analog signal. By generating the lower target voltage, in contrast to a conventional method of generating a maximum target voltage, at the start of the defined interval(s), it is possible to reduce energy waste and help improve efficiency in a power amplifier configured to amplify the analog signal based on the time-variant voltage.

Abstract: A scheme is provided for dynamically adjusting an amount of power drawn from individual power sources to optimize the power usage without violating power limits. Coarse adjustment is provided through dynamic phase reallocation while a fine adjustment is provided through dynamic current steering. By adding a control loop around current steering techniques in digital voltage regulator controllers, power drawn from multiple input rails is balanced. The apparatus allows users to maximize the power delivered to discrete graphics cards without violating PCIe specifications. This allows maximum performance with minimal bill-of-material (BOM) cost.

Abstract: An example system includes a power collection engine. The power collection engine is to convert wireless electromagnetic energy into wired electrical energy. The system also includes a connection management engine. The connection management engine is to communicate with a first transmitter to cause the first transmitter to provide first power to the power collection engine. The connection management engine is to communicate with a second transmitter to cause the second transmitter to provide second power that avoids interference with the first power to the power collection engine.

Abstract: When a signal glitches, logic receiving the signal may change in response, thereby charging and/or discharging nodes within the logic and dissipating power. Providing a glitch-free signal may reduce the number of times the nodes are charged and/or discharged, thereby reducing the power dissipation. A technique for eliminating glitches in a signal is to insert a storage element that samples the signal after it is done changing to produce a glitch-free output signal. The storage element is enabled by a “ready” signal having a delay that matches the delay of circuitry generating the signal. The technique prevents the output signal from changing until the final value of the signal is achieved. The output signal changes only once, typically reducing the number of times nodes in the logic receiving the signal are charged and/or discharged so that power dissipation is also reduced.

Abstract: A power receiver includes a power reception interface that receives wireless power and a controller that transmits an emergency power transmission request for the wireless power during an emergency.

Abstract: Disclosed is a power supply enable circuit. The power supply enable circuit includes a multi-input NAND gate, input terminals of the multi-input NAND gate respectively connected to a plurality of activation signal sources; and a delay circuit, an input terminal of the delay circuit electrically connected to a shared activation signal source of the plurality of activation signal sources. An output terminal of the delay circuit is electrically connected to an enable input terminal of a power supply circuit after performing a logical AND with an output terminal of the multi-input NAND gate.

Abstract: A shift register generates a synthesized pulse having a different pulse width according to which one of a first phase pulse and a second phase pulse is inputted, generates an internal shifted synthesized pulse and a shifted synthesized pulse from the synthesized pulse, and generates a detection signal by detecting a pulse width of the internal shifted synthesized pulse. The shift register outputs the shifted synthesized pulse as one of a first shifted phase pulse and a second shifted phase pulse based on the detection signal.

Abstract: Example proximity sensors are described. The proximity sensor can include a transceiver unit, and a leaky coaxial cable operably coupled to the transceiver unit. The proximity sensor described herein can be used with a steering wheel. For example, the leaky coaxial cable can be embedded in the steering wheel.

Abstract: Methods and devices to mitigate de-biasing caused by an undesired gate induced drain body leakage current in FET switch stacks are disclosed. The devices utilize diode stacks to generate discharge paths for the undesired current. The disclosed teachings are applicable to both shunt and series implementations of FET switch stacks.

Abstract: A power management integrated circuit (PMIC) includes; a DC-DC converter configured to provide output power to a load, a controller configured to control switching of the DC-DC converter, and a sense circuit including a capacitive element and configured to detect an output current flowing through a node between the DC-DC converter and the load.

Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the abovementioned performance improvements are maintained.

Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.

Abstract: An integrated circuit chip and test method thereof are provided. The integrated circuit chip of the disclosure includes a first chip circuit and a plurality of external pins. The first chip circuit includes a plurality of first internal pads, a plurality of second internal pads and a current mirror circuit. The current mirror circuit is coupled to one of the plurality of first internal pads and the plurality of second internal pads. The plurality of external pins are coupled to the plurality of first internal pads.

Abstract: The invention provides an on-chip passive power supply compensation circuit, and an operational unit, a chip, a hash board and a computing device using the same. The on-chip passive power supply compensation circuit comprises: two or more to-be-powered voltage domains, wherein the to-be-powered voltage domains are connected in series between a power supply and ground; and two or more isolation regions, wherein the to-be-powered voltage domains are formed in the isolation regions, and the isolation regions are configured for isolating the to-be-powered voltage domains; the isolation regions are connected in series between the power supply and the ground, wherein the on-chip passive power supply compensation circuit further comprises power supply compensation units connected between the to-be-powered voltage domains and the isolation regions for providing power supply compensation to the to-be-powered voltage domains.

Abstract: Disclosed herein is a charge pump architecture in which boosting capacitors of adjacent stages are connected only by NMOS type transistors and comprising a first stage receiving a first voltage and outputting an internal voltage; a second stage receiving the internal voltage and outputting a second voltage at an output terminal, and an auxiliary stage connected to the output terminal, the first stage and second stage including a first type of MOS transistors transferring the voltage from input node internal boosting nodes and being cross-coupled; a second type of MOS transistors with their gate biased by a third type of MOS transistors and fourth type of MOS transistors; the third type of MOS transistors connecting the gate of the second type of MOS transistors; and the fourth type of MOS transistors connecting the gate of the second type of MOS transistors.

Abstract: A bandgap circuit is disclosed. The bandgap circuit includes a current source configured to generate, using a bias voltage, a first current and a second current, a first bipolar device configured to sink the first current, and a second bipolar device configured to sink the second current via a bias resistor. The bandgap circuit further includes an amplifier circuit configured to generate the bias voltage using a first voltage drop across the first bipolar device and a second voltage drop across the series combination of the bias resistor and the second bipolar device. A compensation circuit is also included, where the compensation circuit is configured to adjust, based on a value of the bias resistor, a base current of the second bipolar device.

Abstract: An LDO regulator includes an error amplifier, a power transistor, a monitoring circuit and/or an adaptive pole adjusting circuit (APAC). The error amplifier compares a reference voltage and a feedback voltage to generate a first error voltage based on the comparison. The power transistor including a gate coupled to an output terminal of the buffer, regulates an input voltage based on a second error voltage which is generated based on the first error voltage to provide an output voltage to an output node. The monitoring circuit, connected to the output terminal of the buffer in parallel with the power transistor, generates a control voltage associated with a load current. The APAC, connected between the output terminal of the error amplifier and the ground voltage, selectively connects an adjusting capacitor between the output terminal of the error amplifier and the ground voltage in response to the control voltage.

Abstract: A circuit for a transmitter driver is disclosed. The transmitter driver circuit includes a main voltage-mode driver circuit configured to receive an input signal at the input port and to drive an output signal at the output port. The transmitter driver circuit also includes a secondary circuit connected to the input port and the output port in parallel with the main voltage-mode driver circuit. The secondary circuit includes: a secondary voltage-mode driver circuit; a current source connected to the secondary voltage-mode driver circuit and controllable to enable or disable a current boost to the output signal; and a switch connected to the secondary voltage-mode driver circuit and controllable to enable or disable the secondary voltage-mode driver circuit to drive the output signal in parallel with the main voltage-driver circuit.

Abstract: A power system may include a plurality of voltage regulator phases each configured to generate an output voltage at its output from an input voltage, a switched capacitor power converter sharing its output with the outputs of the plurality of voltage regulator phases and configured to, when enabled, generate the output voltage at its output from the input voltage, and a power controller configured to selectively enable and disable the switched capacitor power converter based on electrical current requirements of the power system.

Abstract: An on-chip low-voltage current sensing circuit for measuring current in an integrated circuit (IC). In one embodiment, an IC formed on a substrate, which includes a plurality of subcircuits, and a plurality of sensing circuits coupled to the plurality of subcircuits, respectively. The plurality of sensing circuits are configured to generate a plurality of currents, respectively, that are proportional to a plurality of load currents, respectively, consumed by the plurality of subcircuits, respectively, during operation thereof. A circuit is coupled to the plurality of sensing circuits and configured to generate a signal based on an aggregate of the plurality of currents.