Abstract: A sample and hold circuit configured to sample a current includes an input node to receive the current, a capacitor coupled with a sampling node and a reference voltage node, switch between the input node and the sampling node, a controlled current source coupled to the input node, a current mirror circuit having connections each providing a mirrored current, wherein at least one of said connections provides an output node, and a transistor arrangement. The transistor arrangement includes a control MOSFET in series with a series connected chain of cascaded cells. The control MOSFET and each of said cascaded cells are coupled to the current mirror circuit and each of the cascaded cells includes a pair of MOSFETs arranged to provide a voltage difference including a difference between a gate-source voltage of a first of the pair and a gate-source voltage of a second of the pair.

Abstract: Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: conducting a first load current from an upper terminal of the power module to an upper collector-emitter of the transistor, through the transistor, and from a lower collector-emitter to a lower terminal of the power module; and then responsive assertion of a first interrupt signal, interrupting the first load current from the lower collector-emitter to the lower terminal by opening a lower-main FET and thereby commutating a first shutoff current through a lower base of the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor.

Abstract: A current generation circuit includes a metal-oxide-semiconductor (MOS) transistor having a source terminal coupled to one line of a power supply line and a ground line, a voltage generation circuit configured to generate a first voltage corresponding to a resistance value of wiring between the one line and the source terminal, and a control circuit configured to cause the MOS transistor to generate a predetermined current based on the first voltage.

Abstract: An output module for an industrial controller provides electrical isolation between each of the output terminals in the module. The output module receives control signals from the industrial controller indicating a desired output state for each of the output terminals and selectively connects power from the output of the electrical isolation to the output terminal. During normal operation, a switching device connects the power to the output terminal responsive to the control signal. A current sensor monitors the current conducted at the output terminal. If the current exceeds a predefined threshold, a current limit circuit clamps the current being output at the terminal. A control circuit may allow the output terminal to ride through a temporary spike in current or disable the output terminal if a fault condition is detected.

Abstract: The present disclosure relates to voltage regulator circuitry. The voltage regulator circuitry comprises an output device configured to provide a regulated output voltage and a controllable shunt device configured to provide a current path from the output device for a shunt current. The shunt current is variable according to a control signal supplied to the controllable shunt device.

Abstract: An electronic circuit is provided. The electronic circuit includes a first current generating circuit configured to output a first operating current based on a first operating voltage; and an input circuit configured to: receive a first current corresponding to a first input voltage and a second current corresponding to a second input voltage, wherein the first current and the second current are based on the first operating current; receive a third current and a fourth current that are generated based on the first operating voltage; and generate a fifth current corresponding to the second input voltage based on a second operating current. The electronic circuit is configured to generate an output voltage that is associated with a difference between the first input voltage and the second input voltage based on the second current, the fourth current and the fifth current, and the fourth current corresponds to the third current.

Abstract: An electronic device system includes a first electronic device and a power delivery device. The first electronic device is arranged to selectively provide multiple power signals. The power delivery device is arranged to deliver one or more of the power signals. The power signals at least include a first power signal and a second power signal. When the first electronic device detects that the power delivery device is connected to the first electronic device and before a hot plug notification signal is received, the first electronic device provides only the first power signal to the power delivery device. After the first electronic device has received the hot plug notification signal, the first electronic device provides both the first power signal and the second power signal to the power delivery device.

Abstract: A signal generating device includes: a first circuit arranged to generate a first current to a first bipolar junction transistor therein; a second circuit coupled to the first circuit via an output terminal for generating a second current to a second BJT therein; and a first control circuit coupled to the first circuit and the second circuit, for generating a first adjusting current and a second adjusting current to the first circuit and the second circuit for adjusting the first current and the second current such that the first circuit and the second circuit outputs a temperature-dependent signal on the output terminal.

Abstract: A semiconductor device includes m power transistors (m is an integer of 2 or more) coupled in parallel each of which has a sense source terminal, a Kelvin terminal and a source terminal, a first average circuit that connects the first resistor and the second resistor in order between the sense source terminal and the Kelvin terminal and generates first to fourth average voltages and an arithmetic circuit that measures a first current value flowing through the sense source terminal from the first and second average voltages, measures a second current value flowing through the sense source terminal from the third and fourth average voltages and measures a current value flowing through the source terminal from the first to fourth average voltages and the first and second current values.

Abstract: Detecting voltage-based attacks on an integrated circuit (IC) is difficult in the presence of clock jitter. Propagating signals can exhibit a total delay that is due to a delay component resulting from a voltage-based attack and a delay characteristic resulting from clock fluctuation. Voltage-variation detection circuitry includes first and second voltage-dependent circuits and a voltage analysis circuit. The voltage-dependent circuits produce first and second signals that are indicative of a voltage level responsive to a clock signal and based on different first and second voltage sensitivities. The voltage analysis circuit generates a voltage alert signal based on the first and second signals. A combined signal neutralizes the delay characteristic in the first and second signals, but the delay component due to the voltage variation can be at least partially maintained. Thus, a voltage-based attack is detectable in the presence of clock fluctuation by using two voltage-dependent circuits.

Abstract: A radio-frequency module includes a module substrate, a power amplifier, and a control circuit configured to control the power amplifier. The control circuit includes a temperature sensor. The power amplifier and the control circuit are stacked one on top of another on a principal surface of the module substrate.

Abstract: A regulator circuit according to one embodiment includes a first transistor, a filter, and a differential amplifier. The first transistor is provided between an input terminal on a power supply side and an output terminal on an output side. The differential amplifier includes an output node connected to the first transistor, and controls the first transistor on the basis of a result of comparison between a reference voltage and a feedback voltage according to an output voltage applied to the output terminal. The filter is connected to a control node that makes a differential pair with the output node, in the differential amplifier.

Abstract: An error amplifier circuit receives first and second input signals and provides an error amplifier output signal indicative of the difference between the first and second input signals. The error amplifier circuit implements a proportional-integrator-differentiator (PID) circuit having a differential input signal path and including a proportional amplifier circuit, an integrator amplifier circuit, and a differentiator amplifier circuit. The differentiator amplifier circuit receives an AC coupled input signal. The error amplifier circuit sums the output from the proportional amplifier circuit, the integrator amplifier circuit and the differentiator amplifier circuit to provide the error amplifier output signal where the error amplifier output signal is referenced to a first bias voltage.

Abstract: A low dropout voltage regulator includes a differential amplifier configured to output an amplified voltage by comparing a feedback voltage with a reference voltage, a pass transistor configured to receive a power input voltage into a source terminal, the amplified voltage into a gate terminal, and output an output voltage into a drain terminal, distribution resistors connected between the drain terminal and the ground terminal, configured to generate the feedback voltage, and an inrush preventer, connected in parallel between the differential amplifier and the pass transistor, and configured to output a regulated amplified voltage into the gate terminal according to a control signal, wherein the inrush preventer comprises a determiner configured to output an enable signal that is turned on during an initial driving period, and a limiter configured to output the regulated amplified voltage according to the enable signal.

Abstract: A power management circuit operable to adjust voltage within a defined interval(s) is provided. The power management circuit is configured to generate a time-variant voltage for amplifying an analog signal based on a target voltage. In embodiments disclosed herein, the power management circuit can be configured to generate a lower initial target voltage at a start of the defined interval(s), such as during a cyclic prefix (CP) of an orthogonal frequency division multiplexing (OFDM) symbol, and dynamically adjust the initial target voltage, if necessary, within the defined interval(s) based on a time-variant power envelope of the analog signal. By generating the lower target voltage, in contrast to a conventional method of generating a maximum target voltage, at the start of the defined interval(s), it is possible to reduce energy waste and help improve efficiency in a power amplifier configured to amplify the analog signal based on the time-variant voltage.

Abstract: A scheme is provided for dynamically adjusting an amount of power drawn from individual power sources to optimize the power usage without violating power limits. Coarse adjustment is provided through dynamic phase reallocation while a fine adjustment is provided through dynamic current steering. By adding a control loop around current steering techniques in digital voltage regulator controllers, power drawn from multiple input rails is balanced. The apparatus allows users to maximize the power delivered to discrete graphics cards without violating PCIe specifications. This allows maximum performance with minimal bill-of-material (BOM) cost.

Abstract: An example system includes a power collection engine. The power collection engine is to convert wireless electromagnetic energy into wired electrical energy. The system also includes a connection management engine. The connection management engine is to communicate with a first transmitter to cause the first transmitter to provide first power to the power collection engine. The connection management engine is to communicate with a second transmitter to cause the second transmitter to provide second power that avoids interference with the first power to the power collection engine.

Abstract: When a signal glitches, logic receiving the signal may change in response, thereby charging and/or discharging nodes within the logic and dissipating power. Providing a glitch-free signal may reduce the number of times the nodes are charged and/or discharged, thereby reducing the power dissipation. A technique for eliminating glitches in a signal is to insert a storage element that samples the signal after it is done changing to produce a glitch-free output signal. The storage element is enabled by a “ready” signal having a delay that matches the delay of circuitry generating the signal. The technique prevents the output signal from changing until the final value of the signal is achieved. The output signal changes only once, typically reducing the number of times nodes in the logic receiving the signal are charged and/or discharged so that power dissipation is also reduced.

Abstract: A power receiver includes a power reception interface that receives wireless power and a controller that transmits an emergency power transmission request for the wireless power during an emergency.

Abstract: Disclosed is a power supply enable circuit. The power supply enable circuit includes a multi-input NAND gate, input terminals of the multi-input NAND gate respectively connected to a plurality of activation signal sources; and a delay circuit, an input terminal of the delay circuit electrically connected to a shared activation signal source of the plurality of activation signal sources. An output terminal of the delay circuit is electrically connected to an enable input terminal of a power supply circuit after performing a logical AND with an output terminal of the multi-input NAND gate.