Abstract: A scheme may be used to replace a processor in a multiprocessor computer without the need for turning the computer off to replace the processor. In this scheme, all of the processors on the bus are placed into sleep mode. Then, power is disconnected from the processor to be replaced, and the processor is removed. The replacement processor is then powered up and configured in the same manner as the processor it replaced. The replacement processor is then placed into return the computer to normal operation without the need to reboot the computer.

Abstract: A system controller for a controllable system having an inherent time delay includes a delay module that receives a command input and provides a first output signal delayed in time from the command input. A feed-forward module also receives the command input, or a function thereof, and provides a second output signal intended to drive the system to a desired state. A first summer receives the delayed output signal and a feedback signal from the controllable system. The first summer combines the delayed signal and the feedback signal to provide a third output signal. A compensator module receives the third output signal and provides a fourth output signal. A second summer receives the second output signal and the fourth output signal. The second summer combines the second output signal and the fourth output signal to provide an input signal for the controllable system.

Abstract: A method and apparatus for controlling the execution sequence of a first sequence of modules in a first task are provided. The first sequence of modules are linked to one another and have at least one sequence of execution. The method stores in each of the first sequence of modules a skip value representing which of subsequent modules to execute. The method executes the first of the first sequence of said modules, and then executes the next of the modules indicated by the skip value. Conservation of processor bandwidth is accomplished by avoiding the loading of modules which will not be executed. A method and apparatus are further provided for simultaneous activation/deactivation of a set of tasks by a processor, each of the tasks normally executed in a sequential fashion by one or more processors. A list of tasks to be activated/deactivated is stored, including the timing relationship for the activation process.

Abstract: The present invention discloses a system for transparent local and distributed memory management. The invention overcomes the prior art's requirement of keeping track of whether a memory space allocated to a new object or a new program or data structure can be reclaimed. According to the present invention an autorelease pool is created at the beginning of a new duty cycle. The autorelease pool retains the newly allocated memory space during the duty cycle. The autorelease pool is automatically disposed of at the end of the duty cycle. As a result of disposing the autorelease pool, the newly allocated memory space is reclaimed (i.e., deallocated). The present invention is useful in distributed networks where different programming conventions on remote and local machines made the prior art's memory management task particularly difficult. The present invention is also useful in an object-oriented programming environment.

Abstract: An apparatus for programming flash based firmware is disclosed. The apparatus comprises a programmable control card (20) and a processor card (10). The programmable control card (20) includes a control card connector (22) and a programmable flash device (26). The processor card (10) includes a programming connector (12), a processor (16) and on-board flash devices (18). The control card (20) is operable to connect to the processor card (10) by connecting the control card connector (22) with the programming connector (12). Upon starting the processor card (10) control card (20) is operable to transfer programming code to the processor card (10).

Abstract: A method and system for adaptive network security using network vulnerability assessment is disclosed. The method comprises directing a request onto a network. A response to the request is assessed to discover network information. A plurality of analysis tasks are prioritized based upon the network information. The plurality of analysis tasks are to be performed on monitored network data traffic in order to identify attacks upon the network.

Abstract: A time delay from a triggering event to switching of an output signal in a microelectronic device can be adjusted to compensate for various characteristics of the electronic device. The characteristics include temperature, voltage, and manufacturing process conditions. The time delay is adjusted using a variable delay circuit having multiple delay cells that are selectively coupled to control the time delay. The conditions of the electronic device are detected using a process sensor, which includes an oscillator having a frequency that is sensitive to variations in the conditions.

Abstract: Methods for realizing advanced graphical user interface (GUI) in panel subunit. The present invention defines, in one embodiment, a focus in user action and a focus out user action for panel subunit. The focus in/out user actions, when received by a controller device, are then passed to the target device. When the target device receives the focus in/out user actions, the target device will be able to update the GUI appropriately. The present invention also provides a user action pass-through element for conditionally passing through user actions to the target device. In one embodiment, when a scroll button that is implemented with the user action pass-through element is in focus, focus navigation commands received by the controller are passed through to the target device. By using the focus in/out user actions and by using the conditional user action pass-through mechanisms of the present invention, more complicated and advanced GUI, such as an electronic programming guide (EPG) can be achieved.

Abstract: An on-chip programmable delay line is provided for controlling timing of an embedded system. A delay register is coupled to a processor. The delay register stores a delay or control value responsive to the processor. The on-chip programmable delay line is coupled to the delay register and delays a signal responsive to the delay value. The relationship between dynamic random access memory (DRAM) signals, such as row address strobe (RAS) and column address strobe (CAS), can thus be adjusted. In addition, the on-chip programmable delay line can be utilized with a device that includes an input that is not synchronous to a system clock.

Abstract: A method of creating a boot code image in which a computer is configured to fail a boot code creation bypass test. When the bypass test is subsequently executed, an image of a boot code stored in a boot code storage device is copied to a first storage medium. Preferably, the computer is configured to fail the bypass test by inserting at least one jumper in a motherboard of the computer. The boot code creation bypass test is preferably executed in response to a boot event, such as a system power on or reset. In the preferred embodiment, the bypass test comprises a portion of a boot block portion of the boot code. In one embodiment, the boot code is stored to a compact flash card. A flash memory device including a plurality of sectors is used as the boot code storage device. In one embodiment, the boot block and boot code creation bypass test reside in a first sector of the flash memory device while the remaining portions of the boot code including a start up sequence reside in subsequent sectors.

Abstract: The present invention is provided by installing a piece of computer software on a Windows NT system to enable the Windows NT system to bypass messages sent by a Unix system while communications are being established over a phone line between the two operating systems. The Unix operating system has a communications protocol which sends out messages during and requires a password and login to establish communications. The present invention provides a port grabbing routine, a skipping routine, a calling program and a Unix emulator to enable the Windows NT system to establish communications with the Unix system without having to alter the Unix system in any way.

Abstract: An apparatus and a method for storing a BIOS data of a computer system are disclosed. The apparatus includes a first storing apparatus for performing a function as a memory and a function as a storing apparatus for storing a BIOS data therein, a second storing apparatus in which a BIOS data stored in the first storing apparatus is copied and stored therein, a CPU(Central Processing Unit) for accessing a BIOS data stored in the first storing apparatus and driving a computer system when an electric power is supplied to the computer system, a main power controlling for supplying or blocking a main power, a controller for controlling each element of the system, and a system power unit for applying a system power to the first storing apparatus and the controller, respectively, for thereby significantly decreasing the fabrication cost of the system by storing a BIOS data into a SDRAM used as a cache memory of the computer system.

Abstract: A computing system and operating method are executable on a target processor and bootstrap loads and run an application program or interface from an alternative medium, for example a CD-ROM medium or via a network link, when an operating system associated with the application program or interface is not installed on the target processor. For example, a computing system includes an executable program code or command entries that load and run a graphical user interface functionality when the operating system associated with the graphical user interface is not installed. The computing system typically includes a processor, a CD-ROM drive coupled to the processor, and a Random-Access Memory (RAM) Drive coupled to the processor. The executable program code or command entries substitute a designator of the RAM-Drive in place of predefined drive designators that are hard-coded into base code of the operating system.

Abstract: A fault tolerant clock system which employs a plurality of latches each of which is set to fault a clock signal upon the occurrence of one of a like plurality of anomalies and each of which can be independently reset so that the system can be started with asynchronous signals and so that, upon the removal of the anomalies, the latches can be reset to unfault previously faulted signals when the anomaly causing the fault has been cured.

Abstract: A boot code storage device configured with computer instructions for executing a boot code validity check in response to a boot event to facilitate local recovery of a computer such as a network computer. In response to the boot event, such as powering up a computer in which the boot code storage device is located, an image of a boot code is copied from a first storage medium to the boot code storage device if the validity check is negative. Remaining portions of the boot code, including a start up sequence, are executed if the validity check is positive. In one embodiment, the boot code validity check determines the presence or absence of a boot code jumper in a motherboard to which the boot code storage device is connected. In the preferred embodiment, the boot code storage device comprises a flash memory device, preferably including a plurality of sectors.

Abstract: A valve positioner system that includes one or more unique control methods and devices, including several routines to facilitate the continuous maintenance, calibration and adjustment requirements of the valve. The positioner system may utilize pressure and position feedback signals to monitor the valve. The positioner system may utilize an external controller for various diagnostic and other routines. The positioner system can provide automatic positioning and can operate in a manual operating mode or an automatic operating mode. The positioner system can diagnose the valve while the valve process is running or during a maintenance operation. The positioner system can provide nonlinear control of the valve position. The positioner system can self-tune and self-characterize the valve to assure uniform position control. The positioner system can provide valve control through pressure feedback when a position feedback fails or other diagnosed problems.

Abstract: A method and apparatus are provided to establish a network connection for a processor in an operating system-absent environment (i.e., without or prior to an operating system boot). Pre-boot services are first loaded into a volatile memory from a non-volatile memory. These pre-boot services include code for a modem driver. The modem driver code is then used to establish the network connection. In addition, in situations where it is desired to minimize the amount of non-volatile memory required on-site at the processor, the code stored in the non-volatile memory for the modem driver can be limited to only the code necessary to establish a low-speed initial connection. Once the processor is connected to the network, code for a high speed modem driver can be downloaded to the volatile memory of the processor.

Abstract: Methods, systems and computer program products for determining an estimated overall delay value associated with a user's communications with a site in a network and providing the user with a visual representation of this estimated overall delay value are provided. The estimated overall delay value may be determined by estimating the round-trip delay associated with the user's communications with the network site, estimating the transmission delay associated with the user's communications with the network site, and then determining the estimated overall delay value based on the estimated round-trip delay and the estimated transmission delay. The user may be provided the visual representation of the estimated overall delay value by generating an indicia corresponding to the estimated overall delay value and displaying this indicia on the user's display device.

Abstract: An apparatus for automatically selecting a processor clock frequency multiplier is disclosed. The apparatus includes a reset circuit that transmits a reset signal to a processor. When the reset signal is deasserted, the processor samples the states of various strapping signals that are provided by the apparatus. The states of the various strapping signals are determined by a clock frequency multiplier indicator circuit in the apparatus. The apparatus also includes a processor failure detection unit that determines if the processor fails to function properly after reset. If the processor failure detection unit determines that the processor is not functioning properly, the clock frequency multiplier indicator circuit indicates a smaller clock frequency multiplier and a new reset of the processor is performed by asserting the reset signal.

Abstract: A fault tolerant system by which individual components of a server are monitored and controlled through independent, programmable microcontrollers interconnected through a microcontroller network. An external agent can control and monitor the microcontrollers by extending the interconnection network beyond the physical server. The extension to the interconnection network converts protocols between media, and directs the microcontrollers and the state managed by the microcontrollers. Intervention of the server operating system software is not required and is not utilized for the access and control operations. A remote interface board provides the interface between the microcontroller network and an external modem that communicates with a remote client computer. The remote interface board also provides for connection to a local client computer.