Abstract: A phase locked loop is employed to provide a clock signal for controlling the reading or writing of audio data from or into a memory to avoid memory overflow and underrun. The difference between the write and read pointers is monitored and used for adjusting a divider counter used in the feedback loop of the phase locked loop, by incrementing, decrementing by one or leaving unchanged the value of the counter. The counter is used to divide the output of the phase locked loop to provide a reference signal to the phase locked loop. A reference frequency for reading the audio data may be set close to the writing speed by incrementing or decrementing the reading speed by fine adjustment steps until the reference frequency is reached. After the reference frequency is reached, the reading speed is changed between the reference frequency and a frequency one fine adjustment step away from the reference frequency so that the average reading speed is equal to the writing speed.

Abstract: A multiprocessor control system includes a plurality of processors, a boot control device controlling boot of the plurality of processors, a storage device storing boot data therein, and a shared bus interconnecting the plurality of processors, the boot control device and the storage device. The processors constitute at least one boot processor to which the boot data is to be loaded. The boot control device includes a time slot division unit which produces time slots on the shared bus by multiplexing channels for the processors, and a time sharing control unit which determines a time slot for the boot processor among the time slots produced, and assigns the time slot to the boot processor. The time sharing control unit includes a processor interface part which notifies a time-slot location of the time slot determined, to the boot processor.

Abstract: A development system providing a Custom Attack Simulation Language (CASL) for testing networks is described. In particular, the development system implements methodology for facilitating development of network attack simulations. The system includes an editor or authoring system for creating a source code description or Scripts (i.e., CASL-syntax Script) of the simulation program under development. The Scripts, in turn, are “compiled” by a CASL compiler into a compiled CASL program, that may then be used to simulate attacks against a network. CASL makes it easier for users, particularly network and system administrators, to experiment with and learn about the way their networks operate. Since networks work by exchanging packets of information, CASL focuses on allowing users to read and write packets directly to and from the network using a high level programming language.

Abstract: Upon receiving a normal select signal to switch from one clock to another the first clock continues as the output for a number of clock periods. The normal select signal is treated as a disconnect control signal only at the next positive edge of the first clock. The disconnect signal is delayed for a number of cycles and then applied to the control gate of the first clock only when a negative edge of the first clock is detected. Once the disconnect control signal has been issued and the first clock output is dead, the disconnect control signal starts the sequence for connecting the second clock to the output. The connect control signal is accepted at the next positive edge of the second clock, delaying the connect signal for a number of cycles and applying the connect signal to the control of the second clock only when a negative edge of the second clock is detected causing the second clock to disconnect from the output only at a negative edge.

Abstract: A memory system for use in a high-speed computer system, such as a super computer, has synchronous-type storage elements organized in groups for storing data. A storage control section has a clock generator circuit that generates parallel transfer clock signals that compensate for overall transfer delay when data is transferred to the storage elements. Each of the storage elements groups has a phase-locked locked loop circuit that outputs timing signals for accepting data, including address and control signals, etc., at the storage elements. Data is read out from the storage elements to a return data holding circuit of the storage control section using return parallel transfer clock signals, which are controlled by a control section phase-locked loop circuit that receives as an input a timing output of the phase-locked loop circuit of one of the storage element groups. A clock distribution circuit controls the supply of clock signals to a flip-flop group in the return data holding circuit.

Abstract: A channel-to-channel skew compensation apparatus is provided with N number of frame synchronization circuits 11 for generating frame signals to indicate data position of parallel data on a common time axis for each data transmission channel; a reference timing determination circuit 16 for determining a reference timing based on N frame signals output from the frame synchronization circuit 11; a skewing amount detection section 15 for generating N skewing amount signals according to the reference timing determined by the reference timing determination circuit 16; and a timing compensation section 13 for adjusting output timing of parallel data for each transmission channel according to the skewing amount signal generated by the skewing amount detection section 15.

Abstract: A method and system within a symmetrical multi-processing system or information handling system are disclosed for compensating all the processor clocks when performing instruction level tracing. The method provides a simple and flexible mechanism to slow down the clock proportionally to the density of the trace. According to the present invention, the method determines two parameters; a trigger and a compensation step. The trigger is defined as the number of instructions between clock increments and the compensation step is the number of ticks to add to a clock. When the trigger is equal to one, the clock is incremented at each tracing step by an amount equal to the compensation step multiplied by the number of instructions since the last compensation. When the trigger is greater than one, the compensation step is equal to one and the clock is incremented by one every time the number of instructions since the last compensation is bigger than the trigger.

Abstract: A multi-function timer used to perform multiple input timing measurements and generate multiple timed output events on the I/O pins of the apparatus. The multi-function timer comprises a plurality of slots and a compute engine. Each of the slots represents one of a plurality of timing processes. The compute engine includes a micro-sequencer and a processor. The micro-sequencer identifies a current slot and associated plurality of instructions representing a process, and is configured to serially sequence through each of the slots. The processor performs the functions of the instructions associated with each current slot. Further, each slot is configured to perform any one of the following timing processes: pulse width modulation, high speed input, high speed output, or delta time input. The multi-function timer is advantageous in that it provides application design flexibility by eliminating the need for dedicated logic for input and output timing functions.

Abstract: A digital rights management operating system protects rights-managed data, such as downloaded content, from access by untrusted programs while the data is loaded into memory or on a page file as a result of the execution of a trusted application that accesses the memory. To protect the rights-managed data resident in memory, the digital rights management operating system refuses to load an untrusted program into memory while the trusted application is executing or removes the data from memory before loading the untrusted program. If the untrusted program executes at the operating system level, such as a debugger, the digital rights management operating system renounces a trusted identity created for it by the computer processor when the computer was booted. To protect the rights-managed data on the page file, the digital rights management operating system prohibits raw access to the page file, or erases the data from the page file before allowing such access.

Abstract: An improvement in a method of testing a digital circuit or system, having a plurality of scannable memory elements, in accordance with conventional BIST methods in which, at a reference clock, a test stimulus is shifted into the memory elements, the response of the elements is captured and the captured data is shifted out of the elements and analyzed, the improvement comprising controlling the average power consumption of the circuit during the test by suppressing clock pulses from the reference clock during phases of the test that do not require the maximum level of activity or in which the performance of the circuit is not to be evaluated; and, suppressing no clock pulses from the reference clock in phases of the test in which the performance of the circuit is to be evaluated, so that the conditions are substantially as those of normal mode of operation of the circuit.

Abstract: An integrated circuit, such as a microprocessor, which incorporates hardware mechanisms to prevent the circuitry from operating outside the proper bounds of design. The hardware circuitry prevents the microprocessor circuitry from being forced to operate at clock speeds that are greater than it is designed for, from operating at temperatures above or below that which it is designed for, and from being forced to operate at voltages that are above or below voltages that the microprocessor is designed to operate at.

Abstract: One embodiment of the present invention provides a method for aligning a data signal and a data clock signal received from a memory during a read operation. The method includes receiving the data signal and the data clock signal from the memory, and determining an offset between these signals. If the offset is outside of a valid range, the system adjusts a delay between the data clock signal and the data signal. In a variation on the above embodiment, the method is performed by special-purpose hardware located in a memory controller, and operates periodically while the computer system is running. In another variation, the method is carried out by a BIOS program stored in read only memory, and operates during system startup.

Abstract: The identity of an operating system running on a computer is determined from an identity associated with an initial component for the operating system, combined with identities of additional components that are loaded afterwards. Loading of a digital rights management operating system on a subscriber computer is guaranteed by validating digital signatures on each component to be loaded and by determining a trust level for each component. A trusted identity is assumed by the digital rights management operating system when only components with valid signatures and a pre-determined trust level are loaded. Otherwise, the operating system is associated with an untrusted identity. Both the trusted and untrusted identities are derived from the components that were loaded. Additionally, a record of the loading of each component is placed into a boot log that is protected from tampering through a chain of public-private key pairs.

Abstract: A method of interfacing a third circuit with a first circuit that operates based upon a first clock signal and a second circuit that operates based upon a second clock signal includes the step of applying the first clock signal and the second clock signal to a clock selector for the third circuit. The method further includes the step of transferring first data signals between the third circuit and the first circuit at a first rate based upon the first clock signal. Another step of the method includes causing the clock selector to apply the first clock signal to the third circuit prior to the step of transferring the first data signals between the third circuit and the first circuit. Yet another step of the method includes transferring second data signals between the third circuit and the second circuit at a second rate based upon the second clock signal.

Abstract: A method of network surveillance includes receiving network packets handled by a network entity and building at least one long-term and a least one short-term statistical profile from a measure of the network packets that monitors data transfers, errors, or network connections. A comparison of the statistical profiles is used to determine whether the difference between the statistical profiles indicates suspicious network activity.

Abstract: The present invention provides for a data and access protection system for a computer via the use of a hardware key, comprising a non-volatile memory for storing a first access code, a hardware key having a second access code, means for determining whether the hardware key is connected to the computer and whether the first access code is different from the second access code, and means for disabling the computer when the hardware key is not connected to the computer or when the first access code is different from the second access code. Additional aspects of the present invention provide that the hardware key is capable of being carried on a key chain on a person and capable of starting a computer through wireless means. A further aspect of the present invention provides that the hardware key can be used to secure electronic transactions conducted over the Internet.

Abstract: A method and computer program product for simulating, modeling and scheduling equipment maintenance and calibration procedures in a biopharmaceutical production facility is described herein. The method and computer program product includes the steps of identifying maintenance, and maintenance and calibration data associated with biopharmaceutical production process equipment. After the maintenance and calibration data are identified, biopharmaceutical production process equipment is used to generate a table of equipment and maintenance and calibration data. After the table of equipment and data is generated, the table is compared with a procedure time line to determine the schedule of calibration and maintenance for the equipment in the biopharmaceutical production process.

Abstract: A processor has an external pin that can be asserted to lock in new clock ratio information dynamically. A state machine of the processor defines a stop grant state that is utilized to halt the internal clocking signal of the processor. A storage location, such as a register, is utilized to load new clock frequency information into the clock generator circuit of the processor. De-asserting the external pin of the processor causes the processor to resume normal operations, but at the newly set clock frequency.

Abstract: A method and apparatus are provided for performing need based synchronization of a time clock maintained by a computer system. A number of computer systems are connected to a network, such as the Internet. Each computer system synchronizes its time clock by accessing a time server via the network. The time server may service a large number of client computer systems for purposes of providing accurate time of day readings and may therefore be subject to substantial loading. Accordingly, in each client system, the time clock is synchronized at least twice, and an amount of drift in the time clock is determined based on the two or more synchronizations. The synchronization interval for future synchronizations of the clock or the specific time of the next synchronization is then determined based upon the amount of drift, such that the time clock of each client computer system is synchronized only when necessary, and such that the loading on the time server is reduced.

Abstract: A method and apparatus for source synchronous transfers at frequencies including an odd fraction of a core frequency. A disclosed apparatus includes a signal driver circuit and a strobe signal driver circuit. The signal driver circuit is coupled to generate a cycle for a first signal at a first frequency from a core signal from a core operating at a core clock frequency that is an odd fractional multiple of the first frequency. The strobe signal driver circuit is coupled to generate a strobe signal at an intermediate point of the cycle to allow latching of the first signal triggered by the strobe signal.